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This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10−5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.

This paper presents a low-power intermediate frequency (IF) limiting amplifier (LA) and received signal strength indicator (RSSI). The LA and RSSI are designed for ZigBee™ receiver at 2MHz IF. To save power, two local loops for offset correction are used in LA chain and a sensitivity of -56dBm is achieved. Each LA gain stage employs cascade diodes load to avoid driving the diode load into velocity saturation region. The indication rang is 50dB within ±2dB linearity error. The core area is 0.11×0.31mm2 using a SMIC 0.18-μm CMOS technology. The overall power consumption is 1mW from a 1.8V supply voltage.

Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major obstacle has been the poor quality of digitally controlled oscillators (DCO) as MOS varactor Q-factor drops to

This paper presents a novel pseudo-2bit 4GS/s flash analog-to-digital converter (ADC) for an OFDM Impulse Radio Ultra Wide Band (IR-UWB) receiver. Comparing to traditional 2bit flash ADC, it saves a comparator and an encoder. In this ADC, all the signals both in the analog part and the digital part are differential and low swing. A serial-to-parallel module is designed to speed down the output data rate and a Low Voltage Differential Signaling (LVDS) interface circuit has been designed to achieve the data rate as high as 500MSps. The core of the proposed ADC dissipates 26mW power from a 1.8V supply while operating at 4GHz. This chip has been fabricated in 0.18µm 1P6M CMOS process.

Power analysis attack is an important side-channel attack technology. In this paper, a power analysis attack software simulation platform is presented. Three optional schemes with different simulation precision and speed are provided for various requirements and considerations. Simulations of power analysis attacks to several ciphers are carried out successfully on this platform, including block ciphers and public key ciphers.

CLEFIA is a 128-bit block cipher designed newly by Sony Corporation. In this paper, a differential power analysis attack method on every byte of CLEFIA round keys is presented. Through this attack, the round keys can be obtained, and then the 128-bit encryption key can be calculated out. The results of simulation experiments indicate that this attack is effective and practical on the CLEFIA cipher.

In this paper, a fast hardware implementation of multiplicative inversion in GF(2m) using the optimal normal basis of type II is presented. The approach followed is based on the Sunar-Koc multiplier and the Itoh-Tsujii algorithm. Our design is able to compute multiplicative inversion in GF(2233) using only 26 clock cycles.

SMS4 is a 128-bit block cipher used in the WAPI standard for protecting data packets in WLAN. In this paper, various S-box circuit architectures were evaluated firstly and the twisted BDD with m=4 was proved as the fastest one. A fast SMS4 cipher VLSI implementation was completed based on the twisted BDD S-box architecture, and achieved over 200MHz and 100MHz maximal frequency on SMIC 0.18um and Chartered 0.35um CMOS technology respectively.

Since differential power analysis was introduced by Paul Kocher, many countermeasures have been proposed to protect implementations of cryptographic algorithms. Among them, the masking is an efficient method. SMS4 cipher was proved to be vulnerable to first-order DPA attacks, but there has been no countermeasure for it until now. In this paper, we focus on the security of SMS4 implementation, and present a secure implementation of SMS4 cipher with multiplicative masking. Moreover, composite field arithmetic, sharing and reusing hardware resources, and changing calculating orders are employed to produce a small SMS4 circuit. Using SMIC 0.18um CMOS technology, this design requires only about 25 k-gates of area to support both encryption and decryption with 200 Mbps throughput.

This paper presents an integrated 4 GHz divide-by-16/17 dual-modulus prescaler (DMP) with enhanced input sensitivity over extended operation range for ultra-wide band (UWB) transceiver. By modeling the n-stage differential CML D flip-flop ring oscillator based injection-locked frequency divider (ILFD), tradeoffs associated with input sensitivity, locking range and the sizes of the transistors have been derived. Fabricated with SMIC 0.18 mum CMOS technology, the proposed prescaler features enhanced input sensitivity of less than -3 dBm over operation range from 3 GHz to 4.6 GHz. The ratio of the operation range (1.6 GHz) to the maximum operation frequency (4.6 GHz) achieves 35%. The measured phase noise is -110 dBc/Hz at 10 kHz. The core area required is only 0.05mm2. The circuit draws 5.4 mA from a single 1.8 V supply.

Differential power analysis is of great concern because it can be used to break implementations of almost any symmetric or asymmetric algorithm, and several countermeasures have been proposed to protect implementations of cryptographic algorithms except SMS4 cipher. In the present paper, we focus on the differential power analysis attack on SMS4 cipher, and suggest a secure masking scheme for SMS4 cipher, which is particularly suited for implementation in dedicated hardware. The masking scheme for the inversion presented in this article is based on composite field arithmetic, in which the inversion is shifted from GF(28) down to GF(22). In addition, several methods such as module reuse and changing computing order are employed to reduce circuit area and maintain its speed. Using SMIC 0.18 ?m CMOS technology, the area of this improved SMS4 cipher is only about 25 k-gates and the frequency could be up to 50 MHz.

SMS4 is a 128-bit block cipher used in the WAPI standard for protecting data packets in WLAN. In this paper, a differential power analysis attack method on every byte of round keys is presented. Through this attack, the round keys of the last four rounds of SMS4 can be obtained, and then the 128- bit encryption key can be found out. The results of simulation experiments indicate that this attack is effective and practical on the SMS4 cipher.

A new version of Montgomery's algorithm or modular multiplication of large integers is presented in this paper. And a 64-bit parallel carry look-ahead binary adder implemented by SRCMOS (self-resetting CMOS) circuits substitutes for the CPA and one of the two CSAs, which are needed in the previous implementation. And then we can get the modular multiplication result after the loop without the final comparison achieved by making the size of r two nits larger than that of N. In addition, SRCMOS circuits have lower power, faster switching speed and less area than equivalent static CMOS implementations, so we can get a high performance RSA cryptosystem.