Search

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

Wafer thinning has been an important topic in the semiconductor industry. The trend in microelectronic industry is getting thinner and smaller packages. During the process of wafer thinning and sawing, die cracks and thus leading to failures. This problem becomes more significant, when the chip thickness becomes less than 50µm. In this paper, wafer thinning parameters and its effect on the die strength has been reported. A design of experiment (DOE) has been designed to systematically analyze the wafer thinning processes. Established processes for ultra wafer thinning of 40um thickness and die strength characterization results were given in this paper. The wafer sub-surface damages after grinding and stress relieving processed have been reported.