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In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both g m and g D of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed I DS . Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.

In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better I ON -I OFF current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (V G ) and drain current (I D ) as well as the overdrive voltage (V OV ). In addition, the total gate capacitance (C gg ) is also reported.

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR) is exhibited under the gate region thereby improving the device electrical characteristics and the subthreshold properties. Its DIBL and subthreshold swing becomes better compared with its counterpart because the lower source/drain resistance and the wider device effective-width can be obtained. For the same reason, this new device shows a higher transconductance (G M ) behavior. And its drain conductance (G D ) also maintains a good electrical performance with no kink effect compared with the planar-type single top-gate FinFET. With ABR under the gate layer, the lattice temperature is decreased and the thermal instability is alleviated compared with its counterpart.

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (g m ), high cut-off frequency (ƒ T ), and high transconductance generation factor (g m /I d ) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ∼ 60mV/dec, I on /I off ∼ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for JPTGV fabrication and it can be employed for use in deca-nanometer regime.

In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher g m , lower g d , in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting in reduced short-channel effects (SCEs).

In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 I ON /I OFF current ratio.

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.

In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.

This paper presents a highly scalable Π-shaped source/drain (Π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the Π-S/D in the quasi-SOI fabrication that no additional lithography mask is needed due mainly to the isolation-last-formed structures. Hence the advantages of the proposed quasi-SOI over conventional one, in device fabrication, are that the new quasi-SOI process can not only be completely compatible with the standard CMOS process, but can also achieve single-crystal silicon S/D regions. The three-dimensional numerical simulations carried out prove that a modified Π-S/D quasi-SOI transistor can meet ITRS requirements for high-performance devices in the 20 nm technology node and it means that the potential for planar bulk technology can still be used continuously.