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In this paper, an accurate high-frequency modeling methodology for a permanent magnet synchronous motor (PMSM) in a vehicular electrical braking system is presented, which is suitable for analyzing various electromagnetic interference problems caused by a motor drive system. The proposed modeling approach is established according to the vector fitting technique and based on the S-parameter measurements of the PMSM. The equivalent circuit model of the PMSM converted from a measured S-parameter matrix can better describe the impedance characteristics of the three-phase PMSM under study compared to the existing equivalent circuit models because the imbalances inside the motor are taken into account in the proposed modeling process. The proposed PMSM model exhibits high accuracy in the range from 100 kHz to 120 MHz in comparison with the common-mode and differential-mode characteristics of the PMSM, which are measured using the conventional setups.

Far-end crosstalk (FEXT) can reduce the eye opening and eventually decrease the maximum data rate that can be transmitted through the high-speed interconnections. Therefore, FEXT is an important concern in high-speed digital design. The contributors of stripline FEXT include the dielectric inhomogeneity and the proximity effect. In addition, a characterization technique for the effective relative dielectric constant (Dk) of both core and prepreg has been proposed recently for the analysis of the inhomogeneous medium and induced FEXT. In our study, the FEXT levels of the striplines on various printed circuit boards (PCBs) are measured and compared. It is brought to our attention that for some PCB striplines sharing the same stack-up, same PCB material, and manufactured by the same vendor, the corresponding measured FEXT magnitudes of these coupled single-ended traces could vary drastically, which may bring great challenges to the hardware engineers about FEXT level control during the high-volume PCB production phase. In this paper, the root cause of this issue is investigated and analyzed. The “critical resin content percent” concept is proposed to explain the variations in the Dk values of prepreg that result in the FEXT level variance. The full wave simulations are conducted to identify the “critical glass weave”. A measurement-based statistical analysis is performed to verify the “critical resin content percent” concept. A design guideline for FEXT control strategy in the high-volume PCB manufacturing is presented based upon this investigation.

Optical engines co-packaged with switching Application-Specific Integrated Circuit (ASIC) can offer a solution for advancement in bandwidth requirement and are potentially the ultimate direction for the long-touted "optical integration" era. This paper proposes a novel signal integrity (SI) design methodology for package of co-packaged optics (CPO) by using channel operating margin (COM) as a figure of merit (FOM) for the first time. The conventional design method of SI based on individual criteria, such as masks for loss, crosstalk, jitter, eye width/height, impedance, etc., are no longer able to be satisfied at the same time for current high-speed signals up to 50Gbps and even over 100Gbps. COM, combining most of the individual criteria into a single value of signal to noise ratio, provides the possibility to estimate the quality of the channel and achieve a balance between performance and design complexity in the early design stage. In this work, a design methodology in a format of a visible map using the most two significant factors, loss, and crosstalk, to satisfy the required COM is discussed in detail. With this novel methodology, one can predict the SI performance of a package in the early design stage when the real layout has not generated yet for full-wave simulation and can avoid the costly iteration in the conventional design concept.

Far-end crosstalk (FEXT) noise is a critical factor that affects signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCB). Stripline is typically modeled as a 2-layer model with core and prepreg layers. However, in reality, the stripline is laminated by multiple inhomogeneous dielectric layers (IDL). The dielectric layers of the stripline are laminated with epoxy resin and glass bundles. The dielectric permittivity (e r ) of the epoxy resin and glass bundles are different, which causes the inhomogeneity of the dielectric layers while also increasing the FEXT magnitude. Therefore, a typical 2-layer structure is inaccurate to model the FEXT. In this paper, the stripline model is constructed with the core, prepreg, and resin pocket layers. To analyze the stripline with three IDL, a practical superposition method is proposed. A design guideline to mitigate the FEXT level in the stripline design is proposed based on the method.

This paper presents a method for the reduction of mode conversion from differential-mode (DM) noise to common-mode (CM) noise in an unbalanced EMI filter. The unbalanced nature in the EMI filter is a result of not incorporating all the required filter components due to space and cost constraints or due to the parasitic impedances of a printed circuit board (PCB). It is demonstrated that the reduction of mode conversion from DM noise to CM noise can be achieved by modifying the current path on the ground (GND) layer of the PCB of the unbalanced EMI filter. The currents on the GND layer are guided to take a longer route by introducing a "cutout" to the ground plane in the PCB, which increases the impedance of the current path on the GND layer. This approach does not require additional components to the EMI filter for the reduction of CM noise due to the mode conversion. Simulations show that the cutout decreases the CM noise converted from the DM noise by at least 4 dB in the AM radio frequency band (530 kHz – 1.8 MHz).

High-speed PCB design for signal integrity (SI) is about feasible material selection, trace geometry determination and optimization of discontinuities, where the accurate PCB material characterization is essential since incorrect material properties may lead to misleading results and wrong design descisions. The previous studies have revealed that the simulated time-domain reflectometry (TDR) impedance in material characterization, which is based upon the transmission-line-based methods, is erroneous when compared to the measured value, although a good agreement between simulation and measurement in the frequency domain can always be reached. In addition, it is also shown that achieving a satisfactory correlation in both transmission phase and trace impedance is a challenge for SI engineers. This implies that the transmission-line-based approaches, which are widely used in industries, are not perfect and that the extracted PCB material properties are not accurate enough. In this paper, a step-by-step investigation is performed and demonstrated to disclose the root causes of the TDR impedance discrepancy. It is found that the disagreement in TDR impedance is contributed by multiple factors which need to be taken into consideration during material characterization. The improved simulation result exhibits excellent consistency with the measured trace impedance. The suggestions to hardware designers on how more accurate PCB dielectric properties can be obtained are given by addressing the TDR impedance discrepancy issue.

Signal integrity (SI) issue is a critical concern as the data rate continues to increase and SI analysis is heavily dependent on simulations. Inaccurate simulation data may result in inadequate design decisions influencing high-speed digital design and optimization. The surface impedance boundary condition (SIBC) concept is generally utilized in commercial electromagnetic (EM) solvers, which is considered to be an efficient technique as the interior region of the conductor of interest does not need to be included in the numerical procedure. The first-order SIBC has been incorporated into many EM simulation tools widely used in industries. In this paper, the limitations of the first-order SIBC in 2D simulations for PCB transmission lines are analyzed and demonstarted for the first time. Different PCB transmission lines with various cross-sectional geometries are simulated in a commercial 2D EM solver with and without the implementation of the first-order SIBC to reveal the effect on the simulated transmission line behaviors. It is found that the accuracy of the simulations with the first-order SIBC decreases as the edge of the signal conductor in the cross-section becomes narrower. The possible solutions are proposed to overcome the issue.

The increasingly growth of the traffic in data centers demands for high-speed data transition and high bandwidth density. Optical communication is a promising way for the propagation of high-speed signals with less distortions. The quad small form-factor pluggable (QSFP) transceiver module is an essential component converting an electrical signal into an optical signal for point-to-point data transition. Considerable attentions have been paid to the signal integrity (SI) optimization for the optical QSFP transceiver modules with different data rates, where the receiver sensitivity is generally considered to be critical. In this paper, the receiver sensitivity problem of a typical QSFP transceiver module with 10 Gbit/s data rate is studied. It is the first time to demonstrate that the receiver sensitivity improvement is not only related with the SI design, but also connected with the electromagnetic interference (EMI) mitigation inside the DUT. The convential simulation model used for SI analysis with important metal configurations excluded is limited in the ability to identify the coupling between the radiating structures. It is found that the EMI noise induced by the unbalanced PCB routing and the interconnect between the PCB and flexible printed circuit (FPC) has significant contribution to the total noise at the receiver end. The generation of the antenna-mode current is verified and further studied using the full wave simulations. The mitigation method is proposed and confirmed through the measurements to improve the receiver sensitivity.

In electric vehicles, the pulse width modulation scheme is widely used in three-phase motor drive systems for its high performance. However, the fast switching of semiconductor devices may induce excessively high dv/dt and di/dt, which can cause electromagnetic interference (EMI) issues, making it difficult to satisfy electromagnetic compatibility standards. In this paper, the current conducted emission test for a three-phase motor drive system is performed based on CISPR 25 component-level testing setup for AM radio frequency band, which is from 530 kHz to 1.8 MHz. Under these conditions, common-mode (CM) noise generation mechanisms of the motor drive system are identified through measurements. It is found that the dominant mechanism is the mode conversion from differential mode (DM) switching current of the three-phase PWM inverter to CM current through the cable harness due to the imbalances in the PCB structure and EMI filter network which are at the dc input side of the three-phase inverter. Based on this finding, ground (GND) bridges are added between the digital signal and power GND nets to reduce the CM noise. The GND bridge effect on the reduction of CM noise in AM band is experimentally verified and further studied using circuit simulations.

Surface roughness of the conductor in transmission lines will introduce extra losses. The recently proposed Huray model is quite accurate for modeling these additional losses by changing R terms in RLGC models. However, only focusing on the loss modeling of the transmission line may lead to causality issues in time domain simulations. In this paper, the causality requirements of the RLGC models are theoretically analyzed firstly. Then, two solutions of the causality problems in Huray model-based transmission line with rough conductors modeling were proposed and compared. One of them is based on the numerical Hilbert transform, and the other one is analytically based on a complex-valued roughness factor. The causalities of those two solutions are validated by a time domain pulse through a transmission line. The results comparisons of the received pulse responses after the transfer functions show that both methods can improve the causality of the wave propagation term significantly, whereas the analytical solution has better performances and the numerical method has some limitations.

In this paper I-V method-based impedance measurement of power distribution network (PDN) in printed circuit board (PCB) technique is proposed and compared to the traditional VNA method [1]. A I-V method-based probe is designed and verified by comparing the performance with VNA method. To de-embed the parasitic problems, a special I-V probe calibration method is created according to the characteristics of the probe.

SI engineers usually build PCB test coupons and perform cross-sectioning and material properties extraction, and then do design optimization. But designing transmission lines on PCB with good analysis to measurement correlation is really challenging. Although there are some systematic approaches which can be applied to a broad range of applications for highspeed digital designs, it is found that in the validation process, there is always several-ohm mismatch in the comparison of TDR impedance between simulated and measurement results. This degrades engineers' confidence about high-speed design. Taking a real case as an example, this paper is trying to analyze which factors have influence on the trace impedance correlation and showing step by step how the agreement can be improved.

ANSYS Q3D Extractor is a fast quasi-static 3D solver for extracting lumped RLGC parameters and SPICE models. Although Q3D Extractor is faster than full wave simulation, it results in inaccuracies at high frequency simulation, especially for PCB sructures. This paper proposes a method of improving the accuracy of high frequency simulations by using segmentation. For the convenience of study, a transmission line on PCB is selected as the device under test without sacrificing generality, and HFSS simulation results and measurement data are used as reference. Extensive simulations are performed to investigate the effectiveness of segmentation method. It is found that by dividing the transmission line into a set of electrically small segments, the high frequency simulation accuracy can be effectively enhanced. Some other relevant tips for using Q3D are also presented.

Compared to 4-port de-embedding, 8-port de-embedding is much more challenging due to the presence of crosstalk terms in both the differential mode and the common mode. Using the 2nd order mixed-mode concept, this work proposes an 8-port smart fixture de-embedding (SFD) method. The proposed method neglects modal conversion terms by requiring balanced and symmetrical designs. Analysis showed that this approximation generally has negligible impact on the de-embedded differential results with careful test fixture design.

Deployable radiator is a radiation cooling device which is folded next to side wall of spacecraft while launching, and can expand itself after the spacecraft is on track. It can effectively improve the cooling capacity of the spacecraft. In this paper, the current research and development situations of the deployable radiator were studied and analyzed. Depending on this, design and simulation of the deployable radiator based on the loop heat pipe (LHP) was completed, and the experiment was verified in the vacuum environment. The result showed that the thermal experimental results and the thermal analysis data were in good accordance under hot case as well as cold case. Moreover, the temperature oscillations at the shell of the LHP evaporator and the outlet of saturated vapor and the condenser pipeline were found in the experiment. The phenomenon of temperature oscillations was eliminated experimentally by three measures, which included increasing the input heat load, heating the compensation chamber to control the temperature and cooling the compensation chamber.

During the IEC 61000-4-2 test the DUT is placed on a 0.5 mm insulating sheet, which is on the horizontal coupling plane (HCP). For discharge points on the back side of the phone this leads to a situation in which the display is facing the HCP. The phone or tablet forms a capacitance between 50 pF and 300 pF to the HCP. The capacitance value depends on the size of the phone, its screen flatness, and the flatness of the insulator which may deteriorate over time. The discharges to the phone lead to a large displacement current flowing through the display. This current has multiple paths to the body of the phone: via the touch electronics, via the display electronics, and directly to the body of the phone. As these currents can reach 30 A (at 8 kV contact mode) they can lead to upset and damage of both the display and the touch layers. This paper provides analysis of the display down test situation in order to show reproducibility problems. The effect of the capacitance variation is shown by the measurement and the PSPICE model. Full-wave model was used to help understand how much of the total current flows through the body of the phone. The Lichtenberg dust figure method was used to show the contribution of the corona discharge.