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This paper presents a constant bandwidth switched-capacitor programmable-gain amplifier (SC-PGA). By using an adaptive Miller compensation technique for the SC-PGA, our SC-PGA achieves low power consumption and high linearity at various gain conditions. The post-layout simulation results with 0.18 μm CMOS process show that power efficiency is tripled over the SC-PGA without the adaptive Miller compensation technique at 12 V/V gain without degrading performance. Power consumption is 2.8 mW at 3.3 V analog and 1.8 V digital supply voltage.

The proposed 1.8-V 10-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for electrocardiographic (ECG) monitoring applications has two operation modes suitable for the dichotomous activity of ECG signals: full and reduced switching modes. MSBs tracking and LSBs extrapolation run in full and reduced switching mode, respectively, for smooth mode changes adaptive to the input activity. A prototype chip was fabricated in 0.18-μm CMOS technology. The suitability of the proposed adaptive switching was proved by the measurements that the total power consumption was reduced by 15.3% compared to the full switching case.

A high-order temperature compensated current-mode bandgap reference is proposed for automotive applications. The proposed circuit uses one BGR core to produce concave upward and concave downward curvatures which are combined to be compensated and have highly precise current. It also uses two different types of resistors to compensate temperature coefficients in resistors. The circuit is designed specifically for automotive application which operates in a wide temperature range, from −40 C to 150 C. With 3.3-V supply voltage, the simulated output bandgap reference voltage provides a voltage of 861 mV and has a temperature coefficient of 75 ppm/°C. The silicon area is 0.0249 mm2 with a 0.18-μm BCDMOS automotive technology.

This paper presents a low noise output stage of oversampling audio digital-to-analog converter (DAC). The proposed glitchless switched capacitor DAC (GSC-DAC) eliminates the penalty of a constrained signal range and a signal distortion caused by return-to-zero signals in SC-DAC that is an essential part in order to convert the digital signal into the analog signal. By using a track and hold circuit and deglitching method in GSC-DAC, the low noise is efficiently achieved. The results of post layout simulation show the noise performance improvements of 21dB on average of SNR, SNDR, SFDR and THD in comparison with the absence of the proposed techniques.

Many numerical methods are used to solve the point kinetics equations in nuclear dynamics. However the point kinetics equation is characterized by stiff nonlinear ordinary differential equations, which is a severe problem in numerical solution and results in the need for small time steps in a computational scheme. So it is difficult to obtain accurate results. In this work we propose a numerical solution to the point kinetics equations. The proposed method is based on the matrix exponential method under the zero order hold (ZOH) assumption and includes the automatic correction of rounding errors. In order to evaluate the performance, the presented method is compared with Taylor-Lie series with variable inputs.

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a resistor-based offset averaging technique, and a one-zero detecting encoder are proposed. The fabricated chip with 0.1 /spl mu/m CMOS occupies an area of 977 /spl mu/m /spl times/ 1040 /spl mu/m and consumes 145mW at 1.8V power supply. The measured DNL is within 0.5LSB, and the measured SNDR is about 34.55dB, when the input frequency is 10MHz at 2GHz sampling frequency.

In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed track-and-hold (T/H), a novel one-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18/spl mu/m CMOS occupies an area of 977/spl mu/m /spl times/ 1040/spl mu/m and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.