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The field-winding-induced voltage pulsation in the doubly salient brushless dc (DSBLDC) generator leads to the field current ripple and challenges the dc power supply for the field winding. In this article, a new DSBLDC generator with stator-damper winding is proposed to reduce the induced voltage in the dc field winding. The stator-damper winding configuration is illustrated. The winding self-inductance and coupling characteristics are investigated. The influence of the allocation and dimension of the damper winding on the induced voltage suppression as well as the power generation performance is comparatively analyzed. A prototype of the stator-damper winding DSBLDC generator is designed and developed. The experimental results show that the induced voltage of the field winding is reduced by more than 90%, while the output power is nearly close to that of the conventional DSBLDC generator. [ABSTRACT FROM AUTHOR]

We reduce cache supply voltage below the normally acceptable VDDMIN, in order to improve overall many-core system energy efficiency. Based on the observation that cache lines contain mostly one hard faulty cell at these ultra-low supply voltages, we exploit existing double-error correcting triple-error detecting codes, together with cache line disabling, to handle both soft and hard cache faults, thus enabling reliable ultra-low supply voltage cache operation. Compared to the next-best approach in the research literature, the proposed method reduces system energy consumption by up to 25% and energy-execution time product by nearly 10%, while introducing only 0.28% storage overhead and marginal instruction per cycle degradation, when the target yield loss rate is 1/1000. [ABSTRACT FROM AUTHOR]