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Extreme multi-threading and fast thread switching in modern GPGPU require a large, power-hungry register file (RF), which quickly becomes one of major obstacles on the upscaling path of energy-efficient GPGPU computing. In this work, we propose to implement a power-efficient GPGPU RF built on the newly emerged racetrack memory. Racetrack memory has small cell area, low dynamic power, and nonvolatility. Its unique access mechanism, however, results in a long and location-dependent access latency, which offsets the energy saving benefit it introduces and probably harms the performance. In order to conquer the adverse impacts of racetrack memory based RF designs, we first propose a register mapping scheme to reduce the average access latency. Based on the register mapping, we develop a racetrack memory aware warp scheduling (RMWS) algorithm to further suppress the access latency. RMWS design includes a new write buffer structure that improves the scheduling efficiency as well as energy saving. We also investigate and optimize the design where multiple concurrent RMWS schedulers are employed. Experiment results show that our propose techniques can keep a GPGPU performance similar to the baseline with SRAM based RF while the RF energy is significantly reduced by 48.5 percent. [ABSTRACT FROM PUBLISHER]

Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access time, high integration density, nonvolatility, and excellent CMOS integration compatibility. However, similar to all other nano-devices, the performance and reliability of STT-RAM cells are greatly affected by process variations, device operating uncertainties, and environmental fluctuations. As a result, the read and write operations of STT-RAM demonstrate some variabilities and errors. In this paper, we systematically analyze the impacts of CMOS and magnetic tunneling junction (MTJ) process variations, MTJ resistance switching randomness that are induced by intrinsic thermal fluctuations, and working temperature changes on STT-RAM cell designs. The STT-RAM cell reliability issues in both read and write operations are first investigated. A combined circuit and magnetic simulation platform is then established to quantitatively study the persistent and nonpersistent errors in STT-RAM cell operations. Our analysis proved the importance of a full statistical design method in STT-RAM designs for design pessimism minimization. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology due to its various advantageous features such as scalability, nonvolatility, density, endurance, and fast speed. However, the reliability of STT-MRAM is severely impacted by environmental disturbances because radiation strike on the access transistor could introduce potential write and read failures for 1T1MTJ cells. In this paper, a comprehensive approach is proposed to evaluate the radiation-induced soft errors spanning from device modeling to circuit level analysis. The simulation based on 3-D metal-oxide-semiconductor transistor modeling is first performed to capture the radiation-induced transient current pulse. Then a compact switching model of magnetic tunneling junction (MTJ) is developed to analyze the various mechanisms of STT-MRAM write failures. The probability of failure of 1T1MTJ is characterized and built as look-up-tables. This approach enables designers to consider the effect of different factors such as radiation strength, write current magnitude and duration time on soft error rate of STT-MRAM memory arrays. Meanwhile, comprehensive write and sense circuits are evaluated for bit error rate analysis under random radiation effects and transistors process variation, which is critical for performance optimization of practical STT-MRAM read and sense circuits. [ABSTRACT FROM PUBLISHER]

Spin-torque transfer RAM (STT-RAM), a promising alternative to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling down to 45 nm and below, in particular, process variation, introduce the previously unreported and alarming trends in read performance and reliability due to reduced sensing margins and increasing error rates. In this brief, we study the scaling trends of STT-RAM from 65 down to 22 nm as they pertain to read performance, including a 50% increase in sensing versus peripheral circuit delay ratio and a more than 80% increase in uncorrectable read error rates. Through differential sensing, we show how 22 nm can return to sense delay ratio levels at 65 nm and uncorrectable read errors can be reduced by an order of magnitude. Through a case study of a multilevel STT-RAM cache, we show how a reconfigurable cache cell can create an extreme access mode (X-mode) based on differential sensing improve to outperform the state-of-the-art STT-RAM caching techniques in both raw performance and performance per watt by more than 10% while still reducing energy consumption over SRAM caches by more than 1/3. [ABSTRACT FROM AUTHOR]

The development of emerging spin-transfer torque random access memory (STT-RAM) is facing two major technical challenges—poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The evaluations on STT-RAM design metrics and robustness often require a hybrid simulation flow, i.e., modeling the CMOS and magnetic devices with SPICE and macro-magnetic models, respectively. Very often, such a hybrid simulation flow involves expensive Monte Carlo simulations when the design and behavioral variabilities of STT-RAM are taken into account. In this paper, we propose a fast and scalable semi-analytical method—PS3-RAM, enabling efficient statistical simulations in STT-RAM designs. By eliminating the costly macro-magnetic and SPICE simulations, PS3-RAM achieves more than 100 \(000\boldsymbol {\times }\) runtime speedup with excellent agreement with the result of conventional simulation method. PS3-RAM can also accurately estimate the STT-RAM write error rate and write energy distributions at both magnetic tunneling junction switching directions under different temperatures, demonstrating great potential in the analysis of STT-RAM reliability and write energy at the early design stage of memory or micro-architecture. [ABSTRACT FROM AUTHOR]

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potential in embedded and stand-alone applications. However, process variations and thermal fluctuations greatly influence the operation reliability of STT-RAM and limit its scalability. In this paper, we propose a new field-assisted access scheme to improve the read/write reliability and performance of STT-RAM. During read operations, an external magnetic field is applied to a magnetic tunneling junction (MTJ) device, generating a resistive sense signal without referring to other devices. Such a self-reference scheme offers a very promising alternative approach to overcome the severe cell-to-cell variations at highly scaled technology node. Furthermore, the external magnetic field can be used to assist the MTJ switching during write operations without introducing extra hardware overhead. [ABSTRACT FROM AUTHOR]

Recent advances in the emerging memory technology magnetic RAM (MRAM) enrich the opportunities to build high density and low power embedded systems. One common way of utilizing MRAM is integrating it with conventional memories and distributing data to the appropriate type of memory to mitigate the high write penalty of MRAM. In this paper, we propose a software-based approach to identify data access characteristics and guide hardware to perform efficient data distribution. We use our technique to build an on-chip MRAM-SRAM hybrid cache and demonstrate an 86.8% reduction in leakage power, a 9.8% reduction in total power, and a 5% memory performance improvement, compared to a traditional static RAM (SRAM)-only cache. [ABSTRACT FROM PUBLISHER]

Due to its fast access time, high integration density, nonvolatility and good CMOS compatibility, Spin-transfer torque random access memory (STT-RAM) becomes one promising technology for the memory hierarchy of the next-generation computing systems. In recent years, tremendous efforts have been made to reduce the switching current of magnetic tunneling junction (MTJ) for write performance and energy improvement. However, the success of write current reduction makes the STT-RAM read stability issue more prominent during the scaling of STT-RAM: following the decrease in MTJ switching current, the read current must scale accordingly to keep the disturbance on the MTJ resistance state at a minimum level. If the MTJ resistance and/or TMR values do not increase proportionally, the effective sense margin of STT-RAM will degrade, leading to a higher sensing error rate. In this work, we quantitatively analyzed the impacts of existing MTJ scaling rule on the readability STT-RAM, including both read disturbance and sensing errors. We also presented the importance of selecting an optimal read current for maintaining the readability of STT-RAM under the current scaling trend. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed. [ABSTRACT FROM AUTHOR]

By combining the flexibility of MOS logic and the nonvolatility of spintronic devices, Spin-MOS logic and storage circuitries offer a promising approach to implement a highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitries suffers from additional nonpersistent error that incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. In this work, we quantitatively investigate the impacts of the thermal fluctuations on the operations of two typical Spin-MOS circuitries: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile flip–flop design. The possible design techniques to reduce thermal incurred nonpersistent error rate are also discussed. Our experimental results show that the optimization of nonpersistent and persistent errors are closely entangled with each other and should be conducted from both circuit design and magnetic device engineering perspectives simultaneously. [ABSTRACT FROM AUTHOR]

Large switching current and long switching time have significantly limited the adoption of spin-transfer torque random access memory (STT-RAM). Technology scaling, moreover, makes it very challenging to reduce the switching current while maintaining the reliability of magnetic tunneling junction (MTJ) to be similar to that of the earlier generations. In this work, we shall exploit a key insight that in the most on-chip caches where STT-RAM is most likely to be deployed, the lifespan of the data stored in the memory cells is much shorter than the data retention time requirement assumed in STT-RAM development, namely, 4 \sim 10 years. We also quantitatively investigated the possibility of trading off MTJ nonvolatility for improved switching performance, e.g., the switching time and/or current, under architectural level guidance. We further proposed and evaluated a hybrid memory design technique that partitions the on-chip STT-RAM cache into two parts with different nonvolatility performances so as to better fit the diverse retention time requirements of different data sets. [ABSTRACT FROM AUTHOR]