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A Testing system for transient irradiation experiment is designed to explore the transient ionizing radiation effects in an 8bit three state output bidirectional buffer. Signal responses of this circuit irradiated with high dose rate gamma rays are obtained. In particular, changes of output and supply voltage for the circuit are focused. The experiment results show that the recovery situation of signal depends on the disturbance-rejecting capability of supply voltage.

This paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS and PMOS play a role in the SEL happening process. The changes of the drain voltage and the drain current and the functional failure of the circuit were also explained in further. Therefore the new SEL model could be established.

Withscaling applications in the aerospace technology of the large-scale CMOS integrated circuit, the reliability of CMOS device has been the key factor which guarantees the normal work of aerospace equipment. Due to the high-energy particles surrounding the Earth captured by the radiation belt, the CMOS circuits may be hit by them when the aerospace equipment are running around the earth, which may cause single event effects(SEEs). SEEs can make the circuits work abnormally, or even cause serious incidents. Thus it is important to study the influence of SEEs on the CMOS circuit reliability.

The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between RW1 and RW2 or RS1 and RS2 could lead to smaller latch up current and delay more time for the latch up occurrence.

In this paper a single event effect (SEE) fault injection control signal generator based on Monte Carlo method is proposed. Fault control signal generated by the traditional SEE fault injection emulation method for VLSI does not take the speciality of the space environment and the electrical characteristics of the circuit into account. Whereas the signal generator presented in this paper takes advantage of the Monte Carlo method to perform curve fitting on the space particle sample data, as well as to evaluate the circuit node capacitance characteristics and the deposit energy of multiple incidence angles, thereby overcomes the two aspects of disadvantages mentioned before and makes the fault injection emulation approach closer to the real SEE. At the same time C# program and FPGA hardware accelerated emulation are introduced to improve the speed and efficiency of the fault injection control signal generation which makes the proposed generator suitable for generating fault control signal of SEE fault injection emulation.

This paper presents an improved tool called FITVS (Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and FPGA emulation, and the speed of injection can reach the order of lus/fault.