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Examines bit error rates and pulse jitters in rapid single flux quantum logic circuits. Consistency of operation of logic gates and registers; Clock distortion due to timing jitter in Josephson junctions; Timing jitter measurements.

Focuses on the design of a rapid single-flux-quantum switching cryonetwork for petaflops-scale computing. Backpressure and buffering; Throughput and latency of banyan and mesh networks; Modeling and simulation results.

The first version of PSCAN program (Personal Superconductor Circuit ANalyzer) was introduced in 1991. The program is a general purpose superconductor circuit simulator with an emphasis on the design of Rapid Single-Flux-Quantum (RSFQ) circuits. In the intervening years a number of new features were gradually added to the program. In particular, verification of the correct circuit behavior was enhanced using a special hierarchical Single-Flux-Quantum Hardware Description Language (SFQHDL). Next, a fast heuristic algorithm for margin optimization was introduced, which increased the number of parameters that can be simultaneously optimized in reasonable CPU times. Finally, recently we improved the numerical algorithm used for the simulation by using sparse symmetric positive definite matrices (instead of general structure band matrices as before). As a result, simulation speed has increased almost tenfold. Now it takes about 30 seconds of a CPU time on HP716/100 workstation to run a 2000 ps simulation of a 120-Josephson-junction circuit, and about a week to optimize all parameters of a two hundred Josephson junction circuit. We have merged all these improvements in a new version of our simulator, PSCAN'96. [ABSTRACT FROM PUBLISHER]