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3D QLC (Quad-Level-Cell) NAND technology with 16 voltage levels per cell will be one of the next generation memory technologies after 3D TLC (Triple Level Cell) NAND flash succeeded. Besides, program algorithm for 16 voltage levels is studied in this paper, the important read algorithms are investigated because the data errors of QLC device will be easily generated due to power loss, program distribute, etc. The read method with offset and soft message generation for Low Density Parity Check (LDPC) Belief Propagation (BP) soft-decision decoding are presented.

This paper presents a low power 866 MHz injection-locked frequency divider (ILFD) based on UMC 0.18 μm CMOS process. Unlike high-cost off-chip inductor ILFD, on-chip spiral inductor and MOS varactor are used. The ILFD is based on dual cross-coupled LC voltage controlled oscillator (VCO) with direct injection for tail transistor. Compared to NMOS/PMOS-only oscillators, cross-coupled VCO enables low-power operation by doubling transconductance, the supply voltage of cross-coupled VCO can be also as low as 0.6 V. It is about 0.6 mW (without output buffers) under supply voltage of 0.8 V. When the injected input signal power is 0 dBm, direct ILFD features a wide locking range of 100 MHz. The ILFD still has a locking range of 10 MHz when the injected input signal power is −10 dBm. It can be used as the driver stage of power amplifier in transmitter systems for body sensor network.

This paper presents an analog front-end circuit for semi-passive HF RFID tag compatible to ISO/IEC 14443 Type A. System architecture is constructed. The proposed AFE has realized much longer recognition distance than passive tags and can work normally when the magnetic field is 0.3 A/m. It was fabricated with HHNEC 0.13 μm 1P4M CMOS technology with its layout area of 416 μm×472 μm. Measurement results show that this AFE can successfully demodulate the 100% ASK modulated signal and the index of the subcarrier modulation can achieve as high as 16.4%. Its power consumption is as low as 129.6 μW. This chip met the demands of an HF semi-passive tag and made it possible to implant the temperature sensor in the tag.

With mobile and wireless devices becoming pervasive, the low-cost hardware implementations of security functions are being desired. A compact hardware implementation of SM3 hash algorithm is presented in this paper. A SRAM is used to do message expansion function instead of shift registers which are used in common hardware implementations, and the computation units are saved as much as possible. In addition, the values of A∼H and V0∼V7 registers are updated in serial shift way when they are initialized and updated. Compared to traditional designs, the store resources for message expansion function can be shared with other modules to reduce the cost of a system. The Synopsys' DC synthesis results show that the area of the compact SM3 is approximate 9822 GEs while its throughput can be as high as 276 Mbps. If the SRAM can be shared with other modules, only 7806 GEs are additional required to add the SM3 hardware module in the system. The compact architecture can be accommodated to resource-constrained systems for its advantages of low-cost and low-power.

This paper has presented a structure for bandgap reference with wide operating range of temperature by adopting high precision subtractor to eliminate the non-linearization of the TC(temperature coefficient) of V BE . Firstly with the adoption of the technique of curvature compensation, a current with zero TC is obtained. Upon this with the use of subtractor the linear ized V BE is achieved. Furthermore, a mixed topology for the output is adopted to add the linearized V BE to the PTAT (proportional to abstract temperature) voltage so as to obtain an adjustable output voltage. This bandgap based on the process of 0.6µm BiCMOS demonstrates a TC (temperature coefficient) of 4.21ppm/° within the temperature of −50∼140° with the supply voltage of 3.3V and the output voltage of 1V.

An efficiency-enhanced linear LED driver, which operates with a wide input voltage range (6.3 V~32 V) and is able to provide output current up to 350 mA with accuracy of plusmn3%, is presented in this paper. To improve driving efficiency, an operational amplifier is exploited to lower current-sense voltage while PMOS pass element with elaborate metal layout pattern is used to reduce dropout loss. Besides, a 5 V regulated voltage is obtained from the wide range input voltage to supply some modules in the driver so as to further diminish power dissipation of the driver. The proposed driver has been fabricated on a 0.5 mum BCD process occupying 1.4 mm times 1.8 mm area. Post-simulation results show that the proposed scheme driving three HB-LEDs in series can achieve the maximum efficiency of 91.04% at ILOAD=350 mA, which is enhanced by 7.2% compared with that of the typical linear LED driver under the same condition. The dropout voltage is 450 mV when the load current is 350 mA. Besides, it is able to recover within 99 mus.

A novel bandgap reference for minimizing current-mirror mismatch is presented. In the proposed circuit, the small-signal current variations in the two current paths are self-compensated while in the conventional bandgap core they are multiplied. As a result, error caused by current-mirror mismatch has been much reduced in the proposed circuit. Moreover, the voltage variations caused by temperature and supply voltage changes which make the small-signal current in the bandgap core vary can also be minimized. Based on the 0.6 um BiCMOS process technology, the error caused by current-mirror mismatch has been reduced by about 50 times in the proposed bandgap core and the complete circuit achieves a low temperature coefficient of 2.3 ppm/°C and a high power supply rejection ratio (PSRR) of 72 db without any PSRR boosting technique. On typical working conditions, the proposed circuit consumes only a supply current of 3.6 uA.

Non-ideal behavior models of switched capacitor sigma delta ADC are presented. The modulator non-idealities such as operational amplifier parameters (GBW, colored noise, SR, saturation voltage and so on), clock jitter, capacitor mismatch, nonlinear switch on-resistance and are included. The operational amplifier nonlinear DC Gain is modeled with emphasis and simulation results show it introduces odd harmonic distortion.

The advanced encryption standard (AES) S-box was the only non-linear structure of the AES algorithm; it dominated the hardware complexity of the AES cryptographic module. For Wireless Sensor Network applications, S-box must offer low power, small area and high security. In this paper, a full-custom S-box implementation with low-power, compact and well DPA- resistant property was proposed. The energy-efficient pass transmission gate (PTG) and three-input exclusive-OR (XOR) gate based on three-transistor XOR element were used to realize the functionality of S-box, it resulted in the reduction of the area tradeoff and power consumption. The PTG-based latches, controlled by asynchronous latch controllers, were inserted in the data path to block the propagation of the dynamic hazards. A countermeasure against differential power analysis, based on random delay insertion, was presented to attain high-security. The resulting implementation on a 0.25 mum CMOS process is very suitable for the source-limited wireless sensor node chips.

Cryptographic coprocessors for wireless sensor nodes are resource-constrained devices, which require low power and a small size. Besides, with the advent of side channel attacks, resistance to such attacks becomes another major requirement. This paper describes a low-cost and high-security Advanced Encryption Standard (AES) coprocessor implementation and an optimization scheme for Wireless Sensor Networks (WSN) systems. The compact architecture of AES is applied to optimize the size of AES circuits. Its impact on the security against power analysis attack is analyzed, which is important for many WSN applications. A novel method, using inhomogeneous S-Boxes instead of fixed S-Boxes, is proposed to resist power analysis attacks. The AES coprocessor was implemented with UMC 0.25 mum 1.8v CMOS standard cell library and power analysis experiments were conducted. The results demonstrate that our proposed design has very low hardware cost and enhances the AES secure characteristics effectually.

Most of today's wireless sensor networks use a symmetric-key algorithm such as AES for security. Cryptographic S-boxes are an integral part of the AES, although there existed a rich literature devoted to efficient implementations for them, but little attention has been paid to security aspects of the S-box designs. In this paper we conducted a simulation-based CPA attack on AES implementations with different S-box structures. Our results show that the abilities of AES and S-boxes to secure against CPA attack are correlated, and an evaluation of the ability of S-boxes to thwart CPA is presented in a quantitative way. By further exploiting, a novel byte substitution circuit used inhomogeneous S-boxes instead of fixed S-boxes was proposed, and the simulation result shows that power consumption becomes randomized and the peak corresponding to the correct key is masked successfully.

Exploiting composite field arithmetic in Galois field is the common strategy to implement compact S-box. The power consumption of the composite field S-box, however, is too large to be used in wireless sensor network, where both power and area are critical. To find a low-power and compact S-box circuit for targeted applications, a full-custom hardware implementation of asynchronous circuit architecture over composite field is proposed. The pass transmission gates logic is used to realize the functionality of S-box. The low-power latches controlled by the new asynchronous component are inserted in the data processing circuit to eliminate the influence of the dynamic hazards. The resulting circuit can be a hardware Intelligent Property embedded in the wireless sensor node chips, since it dissipates low power consumption and still possesses the compact advantage of the composite field S-box.

How to encode/decode PDUs of protocols is always a time-wasted complicated work in the phase of developing the systems for the telecommunication or internet networks. As ASN.1's well known efficient way to describe the complicated protocols, many protocols PDUs of the presentation layer or the application layer (e.g TCAP, INAP) in the telecommunication network and internet have been represented in ASN.1. One of the key protocols of SS7 network in the legacy telecommunication network is the ISDN user part (short named as ISUP). Its development and extension have an important influence on the related voice telecommunications. However, no ASN.1 presentation file of the ISUP PDUs appears in the ITU-T specifications. One important reason is the special structure of ISUP PDUs against ASN.1 BER which forms the base for the ASN.1 presentation of any protocol PDUs like those PDUs of the protocols (e.g TCAP, INAP, MAP, SNMP). Because of the wide usage of the ASN.1 and the importance of the ISUP, it makes sense to parse the ISUP PDUs with the ASN.1. What's more, there are many open free tools available for parsing to compile ASN.1 into other languages easily, which can ease developing ISUP PDUs parsing tools. In this paper, we present a new effective approach to encode/decode it in the same way as the other protocol PDUs presented in ASN.1. By this approach, we have developed a library available under Linux for parsing ISUP PDUs via ASN.1.

The H.264 video coding standard has achieved a significant improvement in coding efficiency compared to previous standards, such as MPEG1/2/4 and H.261/H.263, whereas its complexity is significantly increased at the same time. In an H.264 encoder, the most time consuming component is variable block size motion estimation. In order to reduce the complexity of motion estimation, a fast block matching motion estimation algorithm is proposed in this paper, which is based on the diamond search (DS) algorithm. This algorithm well exploits the correlation between video sequence motion activity and macro-block coding pattern and motion vector statistic characteristics, judged by rate-distortion optimization rule, so it significantly reduces the search complexity of motion estimation. Experimental results show that the algorithm provides faster search speed than FS and DS algorithm while it provides the almost the same value in PSNR

A 2-Kbit low-power embedded EEPROM memory, which is based on SMIC 0.35 mum three-metal two-poly mixed signal CMOS technology with embedded EEPROM technology, has been developed. Key design techniques of power dissipation optimization for EEPROM memory are described. Optimizations of the current consumption for the charge pump circuit are treated in this paper. To optimize the read access power consumption, a new SA (sense amplifier) using voltage sensing is proposed