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A multilevel differential encoding scheme is proposed as a new approach for use in high-speed parallel transceiver systems. While incurring little or no increase in the number of links, the proposed encoding scheme overcomes two major problems in single-ended parallel links—reference ambiguity and power-line fluctuations. The proposed scheme transmits differentially encoded data among the pins and adjusts the driving current to be constant so as to minimize the L(di/dt) switching noise on the output driver power lines. A new precentering scheme is also applied to maximize the horizontal eye opening by centering all signals during a predefined time before the start of the next symbol transition. To verify the proposed schemes, a transceiver chip was designed and fabricated in 0.25-μm CMOS technology. The chip, which consists of 18 parallel links with only three ground and three supply pins for the output drivers, employs a three-level differential encoding scheme to achieve a maximum data rate of 1.8 Gb/s with a bit error rate of less than 10-12. [ABSTRACT FROM AUTHOR]

Differential phase-shift keying (DPSK) has attracted significant attentions in research and development during the last several years. An overview of DPSK for high spectral efficiency optical transmission is presented in this paper. The advantages of DPSK in terms of receiver sensitivity and tolerance to fiber nonlinearity will be discussed in detail. A simplified method for estimating the performance of phase-shift keying in numerical simulations is explained. Results of experimental and numerical investigations of several phase shift keying formats, including polarization division multiplexing and multilevel encoding, will be reviewed. Finally, methods for further enhancing performance of phase-shift keying in long-haul transmissions, specifically the compensation of nonlinear phase jitter, are presented. [ABSTRACT FROM PUBLISHER]