1. Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays
- Author
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A. Andrade, Florence Azaïs, G. Pereira, Michel Renovell, Marcelo Lubaszewski, Tiago R. Balen, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
- Subjects
Test strategy ,Interconnection ,Computer science ,020208 electrical & electronic engineering ,02 engineering and technology ,Field (computer science) ,020202 computer hardware & architecture ,Set (abstract data type) ,Field-programmable analog array ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Adjacency list ,Graph coloring ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Parametric statistics - Abstract
International audience; The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.
- Published
- 2005
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