1. A low-power high-precision tunable WINNER-TAKE-ALL network
- Author
-
Alan Kramer, Mauro Chinosi, and Roberto Canegallo
- Subjects
Very-large-scale integration ,business.industry ,Computer science ,Analog computer ,Electrical engineering ,Biasing ,500 kHz ,law.invention ,Capacitor ,CMOS ,law ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,business ,Voltage ,Electronic circuit - Abstract
This paper describes a low power CMOS circuit for selecting the greatest of n analog voltages within a tunable selection range. An increasing speed-decreasing precision law is used to determine the amplitude of the selection range. 16 mV to 4 mV resolution, over a 2 V to 4 V dynamic input range, can be obtained by reducing the speed from 2 MHz to 500 kHz. 1 /spl mu/A quiescent current, 2 /spl mu/A AC current for the selected cells and small size make this circuit available for VLSI implementations of massively parallel analog computational circuits.
- Published
- 2002
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