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The paper addresses the scheduling aspects of the problem of synthesizing control-dominated and processor-like systems from their behavioral descriptions. It is demonstrated that global mobility based scheduling can be used for fast design space exploration, generates schedules comparable to those produced by other global scheduling techniques, and can find operations to be moved into the branch delay slot created by a pipelined controller. >

In VLIW (Very Long Installation Word) compilers, one of the most important issues is how to handle conditional branches, because control dependences are caused by conditional branches and limit the scope of scheduling. This paper proposes the efficient method of eliminating conditional branches. We use SSA (Static Single Assignment) information for preserving semantics. By using our methods, global scheduling techniques can be processed more efficiently and simply. We utilize /spl phi/-functions aggressively, thus computations for code motion are not required. We don't need complex hardware support. Our scheme also makes the performance independent on the result of branch outcomes.

The authors describe a novel algorithm that combines the hardware scheduling and component selection phases for high level synthesis. The algorithm improves on previous work in scheduling, by being able to simultaneously select components from a given library. This enlarges the design space, resulting in better optimized designs. Experimental results on the elliptic filter benchmark demonstrate that exploiting all available components in the library results in designs with smaller area compared to designs produced by scheduling with a single implementation for each component type. >

The authors describe how code is restructured to enhance application performance on the Intergraph C400. The restructuring has several aims: to avoid or to reduce pipeline stalls, to enhance register and cache utilization, and to optimize control flow to reduce branch overhead and improve instruction scheduling scope. Avoiding pipeline stalls is a matter of locally and globally reordering computations so that the results are available before any attempt to use them. Improving register and cache utilization is done by restructuring algorithms to do as much as possible on data elements while they are held in registers or cache. In both these cases, the restructuring is controlled by dependence analysis similar to that found in vectorizing/parallelizing compilers. Branch overhead is reduced and instruction scheduling is improved by optimizing the block ordering of the program around the most frequently executed paths. >

Discusses the use of run-time feedback for optimizing the execution of parallel computations. Four levels of feedback are distinguished and the applicability and limitations of each are discussed. A two-part scheduling paradigm known as SEDIA (Static Exploration/Dynamic Instantiation and Activation) that addresses these limitations to perform robust scheduling in the presence of variant run-time behaviour is introduced. A key component of this scheduling paradigm is an abstract model of run-time information fidelity, which has evolved from our previous work in the area of trace recovery, employing control-theoretic concepts.