1. Impact of Interconnect Multiple-Patterning Variability on SRAMs
- Author
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Karageorgos, Ioannis, Stucchi, Michele, Raghavan, Praveen, Ryckaert, Julien, Tokei, Zsolt, Verkest, Diederik, Baert, Rogier, Sakhare, Sushil, Dehaene, Wim, Nebel, Wolfgang, and Atienza, David
- Subjects
interconnects ,variability ,Back End of Line ,multiple patterning ,SRAM ,variation aware design ,LELE ,multi patterning ,BEOL ,EUV ,Self Aligned ,SADP ,variation ,process variation - Abstract
The introduction of Multiple Patterning (MP) in sub-32nm technology nodes may pose severe variability problems in wire resistance and capacitance of IC circuits. In this paper we evaluate the impact of this variability on the performance of SRAM cell arrays based on the 10nm technology node, for a relevant range of process variation assumptions. The MP options we consider are the triple Litho-Etch (LE^3) and the Self Aligned Double Patterning (SADP), together with Single Patterning Extreme-UV (EUV). In addition to the analysis of the worst-case variability scenario and the impact on SRAM performance, we propose an analytical formula for the estimation of SRAM read time penalty, using the RC variation of the bit line and the array size as input parameters. This formula, verified with SPICE simulations, allows a fast extraction of the statistical distribution of the read time penalty, using the Monte-Carlo method. Results on each patterning option are presented and compared. ispartof: pages:609-612 ispartof: Proc. DATE vol:2015 pages:609-612 ispartof: Design, Automation and Test in Europe Conference and Exhibition (DATE) location:Grenoble, France date:9 Mar - 13 Mar 2015 status: published
- Published
- 2015