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Funding Information: This work was supported in part by the Business Finland through 5WAVE Project, and in part by the Academy of Finland through ADENN Project. The work of Sabin Kumar Karki was also supported in part by the Nokia Foundation, and in part by the Walter Ahlström Foundation. The work of Mikko Varonen was also supported by the Academy of Finland Research Fellow Project under Grant 310234. Publisher Copyright: © 2013 IEEE. Copyright: Copyright 2021 Elsevier B.V., All rights reserved. A beam-switching array is designed using a $4\times 6$ Rotman lens as a beam-forming network to switch the beam towards -30°, -10°, 10°, and 30°. Six substrate integrated waveguide fed $1\times 4$ microstrip patch arrays are used as the radiating elements. The beam-switching array is designed on the LTCC substrate to operate at 71-76 GHz. In this work, the feasibility of implementing a beam-switching network with a vector modulator (VM) integrated circuit as switching element is studied for the first time. The measured radiation pattern of the beam-switching array with the VM is in line with the simulated radiation pattern. The measured peak realized gain of the beam port 1, 2, 3, and 4 with 3-dB backoff gain of the VM are 17, 17, 17.8, 16.9 dBi at 75 GHz, respectively. In addition, the work demonstrates the possibility of beam-reconfigurability in beam-switching array by simultaneous excitation of the beam ports in optimum phase using the VM. The simultaneous excitation of the adjacent two ports, 1-2, 2-3, and 3-4, steer the beam towards -19°, 0°, and 19°, respectively, which improves the beam cross-over level. With various combinations of simultaneous excitation, the half power beam-width of the beam-switching array is varied from 17.8° to 75°.

This paper presents a digitally controlled vector modulator integrated circuit aimed for millimeter wave phased array systems. The vector modulator operates over 60-100 GHz range covering 360 degree phase and over 10 dB gain control ranges. The maximum gain of 35.6 dB is achieved at 96.8 GHz. The chip is processed in 0.13 μm silicon germanium technology. Size of the chip including the pads is 2.1 × 0.7 mm2 from which the vector modulator core occupies 0.45 × 0.30 mm2.

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.