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The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

Influence of the gate module on the channel stress in [Si. Sub. 1-x] [Ge.sub.x] and [Si.sub.1-y] [C.sub.y] S/D MOS transistors are studied by simulation tests. Metal gates of 1nm thickness are found to influence stress generation and the removal and redeposition of polysilicon layer without changing the underlying metal gate increases the stress but not to the extent of complete gate removal.

The analysis of the junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication is described. The studies have shown that the area-junction static-power consumption for the best junctions has remained below the power-density specifications for high-performances applications.

The quality of ultrathin SiON dielectrics of n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) grown on strained-Si layers with both thin and thick SiGe strain-relaxed buffers (SRBs) is examined. Results suggest that the gate leakage in the strained-Si samples was of a trap-assisted nature and temperature-dependent.

The fabrication of long-channel Ge transistors with a high-k dielectric and a hole mobility more than 2.5 times the Si/Si[O.sub.2] universal at vertical effective fields up to 1 MV/cm is reported.

A study on the effectiveness of strained contact-etches-stop-layer (CESL) technologies in aggressively scaled dense structures is presented. Results show that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations.

The performance and reliability between polysilicon gate/SiON oxide nano metal-oxide semiconductor field-effect transistors (nMOSFETs) is compared with and without SiN cap layer. The robustness against hot carrier stress, bias-temperature instability and time to breakdown are seen between strained and unstrained-silicon devices, thereby confirming the advantages of strain technology.

The layout dependence of the silicon-germanium source/drain {[Si.sub.1-x][Ge.sub.x] S/D} technology is studied for the 45-nm technology node and beyond. The nested transistor, where other gates surround a polygate and isolated transistors, where the active area is completely surrounded by isolation oxide are two technologically important configurations investigated.

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates is analyzed. A better 1/f noise performance can be achieved using SSi substrates and some dedicated defect-assisted noise-generating mechanisms are identified, which are related to nonoptimized processing conditions.