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An automated code restructuring strategy is presented for reducing the number of off-chip references for a set of parallelized array/loop-intensive applications running on cache-memory-based multiprocessor-system-on-a-chip (MPSoC) architectures. Findings reveal the excellent performance of the proposed strategy.

A compiler-driven approach proposes the disk layout information to the compiler for getting the order in which parallel disks are accessed. The compiler-driven proactive approach to disk power management is better in performance.

The problem of estimating and reducing the amount of memory needed for transfers of data in embedded systems is addressed. Embedded systems that process data arrays in signal processing codes are needed throughout the execution program.

An adaptive loop parallelization strategy is evaluated and the potential energy savings when unused processors during execution of a nested loop are shut down is measured. The results show that shutting down unused processors can lead to approximately 67 percent energy savings at the expense of up to 17 percent performance loss in a set of array-intensive applications.

Dynamic layout optimization strategy called quasidynamic layout optimization is introduced to minimize the number of cycles spent in memory accesses. Significant improvements are indicated in execution time over static layout-based locality enhancing techniques.

The object serialization feature of Java is used to allow offloading of both method execution and byte code-to-native code compilation to the server. This allows the mobile client to conserve energy when using Java-enabled wireless devices.

A data-driven strategy to optimize the memory energy consumption is taken up in a banked memory system, as improving memory energy is an important consideration. The results indicate that the proposed strategy is successful in reducing the memory system energy and improves memory energy by as much as 36.8 percent over the other strategies.

The design, implementation and evaluation of a novel application development environment for scientific computations are discussed. This environment makes it easy for the programmers to code and run their applications without much programming effort.

A mathematical framework is presented for dealing with the interaction between false sharing and locality for programs on shared-memory multiprocessors.

Software optimization techniques are examined. Their effects in five different I/O-intensive applications is evaluated.

The effects of several I/O optimization techniques on the performance of five I/O-intensive applications are investigated.

A compiler-directed collective I/O procedure is described, for dealing with I/O latencies of large-scale scientific codes. Experimental results show that the approach works well, using various benchmarks.

A technique based on integer linear programming (ILP) is proposed for deriving the best combination of loop and data layout transformations.

One-way communication was examined in the context of minimizing data and synchronization costs.

A framework is presented for optimizing out-of-core programs using locality and parallelism. In the study, the compiler is fully in control of the placement of I/O calls.

A study was conducted to analyze a data layout optimization method for sequential and parallel computer programs based on the concept of hyperplanes from linear algebra. The technique automatically obtains appropriate memory layouts that can be determined by hyperplanes for referenced arrays. The premise that data transformations can maximize spatial locality for some arrays was also examined.