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Common subexpression elimination (CSE) technique is regarded as one of the popular methods to minimize the number of logic operators (LOs) in digital filter by eliminating the redundant occurrence of bit pattern. To this aim, this brief presents an innovative triangular CSE algorithm that generates FIR filters with reduced number of logic operators when compared to other CSE techniques in the literature. Supremacy of our design strategy has also been established in terms of logic operators and logic depths over a number of state-of-the-art techniques of recent interest. Simulation results have offered a noticeable average LO reduction when compared with other related algorithms. Supremacy of the proposed design has also been substantiated by implementing the filters on Cyclone IV FPGA chip.

Design of hardware efficient digital systems has drawn appreciable attention of researchers over the last few decades. To this aim, this paper considers the design of a narrow transition band finite impulse response (FIR) filter operated in an interpolated bandpass filtering approach. An optimization problem is formulated that minimizes the complexity measure of the narrow transition band FIR filter under the constraints of length of the filter and normalized peak ripple magnitude (NPRM) threshold. Closed-form expressions for the optimal interpolation factor as well as the passband and stopband edges to obtain the narrow transition band are derived. A designed filter is subsequently implemented on Altera’s Cyclone IV field programmable gate array (FPGA) chip and supremacy of the suggested design has strongly been established by correlating its hardware cost with many of the state-of-the-art FIR filters.

This paper proposes a new technique, called conditional differential coefficients method (CDCM), for hardware-efficient realization of finite impulse response filters using differential coefficients. In connection to this, a group of differential coefficients are extracted from the entire set which aims to reduce the total number of ones in the coefficient representation. Selection of the differential coefficients has been done in accordance with its difference with the original coefficient. It has the consequent effect of minimizing the total number of full adders with respect to direct method, minimum index floating point representation scheme, minimal difference DCM, and so on.

The role of stochastic variations in pad surface topography evolution during a chemical-mechanical planarization or polishing (CMP) process is investigated. The roughness of the pad surface is considered, while the blanket film wafer is smooth and flat. The material removal rate (MRR) for CMP is modeled utilizing elastic as well as inelastic contact between the wafer and pad. Evolution of the pad surface topography is observed to have a significant influence on the MRR variations. A distinguishing feature of this paper is the MRR evolution equation for a single asperity. It is observed that an elastic contact model significantly underestimates the experimental trend. The selection of the initial probability density function (pdf) used in an MRR time-evolution model is shown to be a key issue. It is observed that reasonably small changes in numerical estimates of pdf parameters can have a significant effect on the accuracy of material removal model predictions. By extending the model to the case of inelastic contact between the wafer and pad asperities, it is found that model performance can be notably improved. Finally, it should be mentioned that the emphasis here on statistical elements, combined with the approach of developing mean MRR models based on models for individual asperities, allows one to easily incorporate more realistic model assumptions, an example being that pad asperities have tip curvatures and spacing that are random.

An analytical model for dishing and step height reduction in chemical mechanical planarization (CMP) of copper is presented. The model is based on the assumption that at the feature scale, high areas on the wafer experience higher pressure than low areas. The slurry is assumed to be Prestonian. The model delineates how dishing and step height reduction depend on slurry properties (selectivity and Preston’s constants), pad characteristics (stiffness and bending ability), polishing conditions (pressure, relative velocity and overpolishing) and wafer surface geometry (linewidth, pitch and pattern density). Model predictions are in good agreement with existing experimental observations. The present model facilitates understanding of the CMP process at the feature scale. Based on the proposed model, design avenues for decreasing dishing and increasing the speed of step height reduction may be explored through modification of appropriate parameters for slurry, pad and polishing conditions. The proposed model may also be used as a design tool for pattern layout to optimize the performance of the CMP process.Copyright © 2002 by ASME

It is well known that the chemical reaction between an oxide layer and a water-based slurry produces a softer hydroxylated interface layer. During chemical-mechanical polishing (CMP), it is assumed that material removal occurs by the plastic deformation of this interface layer. In this paper, the behavior of the hydroxylated layer is modeled as a perfectly plastic, material, and a mechanistic model for material removal rate (MRR) in CMP is developed. The deformation profile of the soft pad is approximated as the bending of a thin elastic beam. In addition to the dependence of MRR on pressure and relative velocity, the proposed plasticity-based model is also capable of delineating the effects of pad and slurry properties. The plasticity-based model is utilized to explore the effects of various design parameters (e.g., abrasive shape, size and concentration, and pad stiffness) on the MRR. Model predictions are compared with existing experimental observations from glass polishing, lapping, and CMP.

Interfacial shear stress, peeling stress, and die cracking stress due to thermal and elastic mismatch in layered electronic assemblies are one of the major causes of the mechanical failure of electronic packages. A simple but rather accurate method is developed to estimate these thermal stresses for packages with different layer lengths. For layered electronics with thin adhesives, analytical expressions are obtained for interfacial shear stress and peeling stress, and they agree well with the finite element analysis, especially when the moduli of adhesive layers are significantly lower than the moduli of the other layers. An analytic expression of die cracking stress is also obtained for multilayer electronic assemblies.