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This paper extends N-path filtering to the code domain by proposing code-modulated local oscillator signals. A correlator-based perspective of N-path mixer receiver (RX) is presented to demonstrate interferer-rejection and desired signal reception in a code-domain N-path RX. Pairs of Walsh-function-based codes are proposed for modulating desired RX and known interferers [such as self-interference (SI) from transmitter (TX)] to achieve high interferer rejection. An N-path architecture for concurrent reception of two code-modulated signals is also presented. A 0.3–1.4-GHz 65-nm CMOS implementation achieves 35-dB gain for desired signals and concurrently receives two RX signals while rejecting mismatched spreading codes at RF input. The proposed TX SI mitigation approach results in 38.5-dB rejection for −11.8 dBm 1.46-Mb/s quadrature phase-shift keying (QPSK) modulated SI at the RX input. The RX achieves 23.7-dBm output referred 1dB gain compression (OP1dB) for in-band SI, while consuming ~35 mW and occupies 0.31 mm2. Such code-domain selection/rejection can be used in conjunction with other N-path filtering schemes for signal selection/rejection based on a combination of spatial, spectral, and code-domain properties.

Impedance translation using passive N-path mixers has been used to achieve local oscillator (LO)-defined series bandstop and shunt bandpass filtering. In this paper, we generalize N-path filtering using a correlator-based approach and propose N-path passive mixers driven by orthogonal sequences. Such sequence-driven N-path filters can potentially reject or select signals based on their properties in the spectral, spatial, and code domains. Specifically, a Walsh-function (WF) sequence (WF-seq)-based N-path shunt filter is implemented, demonstrating the feasibility of shunt bandstop filtering using LO sequences other than nonoverlapping pulses. The WF-seq approach enables reconfigurable concurrent filtering at two different frequencies with shunt operation avoiding penalties due to the switch drive overlap. A 65-nm CMOS implementation achieves 20-dB rejection at one frequency and 14-dB rejection concurrently at two frequencies between 0.3 and 1.4 GHz. The reconfigurable bandstop filter is implemented using analog gyrators and consumes 35–62.5 mW and achieves 2.9-dB noise figure and −2.5–5-dBm IIP3.

Integrated oscillators with octave frequency tuning range (FTR) are desirable for wireless transceivers supporting multiple frequency bands. In this paper, we describe a wide-FTR CMOS voltage-controlled oscillator (VCO) based on a novel area-efficient series resonator mode-switching scheme that preserves resonator quality factor $Q$ across the entire octave tuning range. This allows the CMOS VCO to simultaneously achieving wide FTR, area efficiency, and low phase noise, demonstrating state-of-the-art figure of merit (FoM) for > 10-GHz octave-tuning range VCOs. We also analyze the relationship between $Q$ and FTR across common resonator band-switching schemes, quantifying performance limits and highlighting the benefits of using mode-switching for wide-FTR VCOs. The proposed approach is demonstrated through a 6.4–14-GHz (74.6% FTR) VCO implemented in 65-nm CMOS that achieves 186–188-dB VCO FoM, demonstrating good FoM across the entire FTR. The scalability of this approach toward achieving even larger FTR is also demonstrated by a triple-mode 2.2–8.7-GHz (119% FTR) CMOS VCO. Area efficiency of the proposed mode-switching scheme is demonstrated by the state-of-the-art 197-dB FoM area achieved by the 14-GHz VCO.

Advances in CMOS and SiGe technologies have made millimeter (mm)-wave multielement arrays with complex architectures, high yields, and good interelement matching feasible. However, the antenna-in-package approach is challenging with a larger number of array elements due to the increase in mm-wave I/O, the need for impedance-controlled via/routing symmetry. In this work, we describe an antenna-IC cointegration approach that relies on aperture coupling between on-chip feed/ground-plane slot and an antenna-on-substrate to simultaneously achieve wide bandwidth and high efficiency. The proposed approach is validated through a 60-GHz packaged prototype in which a 60-GHz quadrupler and aperture-coupled antenna feed fabricated in a 0.18- $\mu \text{m}$ SiGe technology is cointegrated with a 60-GHz patch antenna on a 100- $\mu \text{m}$ liquid crystal polymer substrate. Measured E-plane and H-plane antenna patterns show 0-dB gain at 61 GHz (corresponding to 40% efficiency) and cross-polarization ratio of $\sim$ 10 dB, demonstrating the feasibility of the proposed approach.

The emergence of battery-constrained system-on-chip (SoC) devices, such as smartphones and tablets, requires hardware/software codesign to optimize battery life. Offloading activities from the processor to specialized engines on the SoC can help reduce power consumption.

Software behavior can significantly affect computer energy efficiency in everything from small devices up to servers in data centers. However, there are multiple techniques that software developers can use to reduce the energy consumption of drivers and applications.

A low-distortion active filter is realized using current-efficient feedforward-compensated operational amplifiers in the integrators and feedforward current injection in the summing amplifier. A third-order elliptic low-pass filter with two possible bandwidth settings of 17 and 8.5 MHz consumes 1.8 mW from a 1.8-V supply and occupies 0.17 ?m2 in a 0.18- ?m CMOS process. The measured maximum signal-to-noise and distortion ratios at the two bandwidth settings are 50.5 and 52.5 dB, respectively. The corresponding third-order intermodulation intercept points (IIP3) are +28.2 and +30.8 dBm. Automatic tuning is used at the startup to counter process variations and set the bandwidth accurately. � 2011 IEEE.