45 results on '"Beyne, Eric"'
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2. Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects
3. Efficient Characterization of Interconnects With Arbitrary Polygonal Cross Sections Using Fokas-Derived Dirichlet-to-Neumann Operators
4. NimbleAI: towards neuromorphic sensing-processing 3D-integrated chips
5. NimbleAI: towards neuromorphic sensing-processing 3D-integrated chips
6. Analysis and Application of a Surface Admittance Operator for Combined Magnetic and Dielectric Contrast in Emerging Interconnect Topologies
7. Reliability Challenges in Advanced 3D Technologies: the Case of Through Silicon Vias and SiCN–SiCN Wafer-to-Wafer Hybrid-Bonding Technologies
8. Efficient Backside Power Delivery for High-Performance Computing Systems
9. 84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor
10. System Optimization: High-Frequency Buck Converter With 3-D In-Package Air-Core Inductor
11. Area-Selective Electroless Deposition of Cu for Hybrid Bonding
12. Power from Below: Buried Interconnects Will Help Save Moore's Law
13. Reliability Study of Polymers Used in Sub-4-μm Pitch RDL Applications
14. Experimental and Numerical Study of 3-D Printed Direct Jet Impingement Cooling for High-Power, Large Die Size Applications
15. Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy
16. Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects
17. Entire Domain Basis Function Expansion of the Differential Surface Admittance for Efficient Broadband Characterization of Lossy Interconnects
18. A Novel Intermetallic Compound Insertion Bonding to Improve Throughput for Sequential 3-D Stacking
19. Low-Cost Energy-Efficient On-Chip Hotspot Targeted Microjet Cooling for High- Power Electronics
20. A Novel Resistance Measurement Methodology for $In~Situ$ UBM/Solder Interfacial Reaction Monitoring
21. Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs
22. Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes
23. Experimental Characterization of a Chip-Level 3-D Printed Microjet Liquid Impingement Cooler for High-Performance Systems
24. High-Efficiency Polymer-Based Direct Multi-Jet Impingement Cooling Solution for High-Power Devices
25. Expected Failures in 3-D Technology and Related Failure Analysis Challenges
26. Anomalous ${C}$ – ${V}$ Inversion in TSVs: The Problem and Its Cure
27. Investigation of Co Thin Film as Buffer Layer Applied to Cu/Sn Eutectic Bonding and UBM With Sn, SnCu, and SAC Solders Joints
28. Statistical Distribution of Through-Silicon via Cu Pumping
29. Convolution-Based Fast Thermal Model for 3-D-ICs: Transient Experimental Validation
30. Performance and Reliability Impact of Copper Plasticity in Backside TSV-Last Fabrication Process
31. Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration
32. The 3-D Interconnect Technology Landscape
33. Reliability Challenges Related to TSV Integration and 3-D Stacking
34. Fine Pitch Rapid Heat Self-Aligned Assembly and Liquid-Mediated Direct Bonding of Si Chips
35. Fast Transient Convolution-Based Thermal Modeling Methodology for Including the Package Thermal Impact in 3D ICs
36. System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform
37. Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits
38. Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits
39. Novel Cu–Cu Bonding Technique: The Insertion Bonding Approach
40. Technology Assessment of Through-Silicon Via by Using $C$–$V$ and $C$–$t$ Measurements
41. 3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias
42. Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications
43. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
44. High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA
45. A generic methodology for deriving compact dynamic thermal models, applied to the PSGA package
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