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Data centers are increasingly using high-speed circuit switches to cope with the growing demand and reduce operational costs. One of the fundamental tasks of circuit switches is to compute a sparse collection of switching configurations to support a traffic demand matrix. Such a problem has been addressed in the literature with variations of the approach proposed by Birkhoff in 1946 to decompose a doubly stochastic matrix exactly. However, the existing methods are heuristic and do not have theoretical guarantees on how well a collection of switching configurations (i.e., permutations) can approximate a traffic matrix (i.e., a scaled doubly stochastic matrix). In this paper, we revisit Birkhoff’s approach and make three contributions. First, we establish the first theoretical bound on the sparsity of Birkhoff’s algorithm (i.e., the number of switching configurations necessary to approximate a traffic matrix). In particular, we show that by using a subset of the admissible permutation matrices, Birkhoff’s algorithm obtains an ǫ-approximate decomposition with at most O(log(1/ǫ)) permutations. Second, we propose a new algorithm, Birkhoff+, which combines the wealth of Frank-Wolfe with Birkhoff’s approach to obtain sparse decompositions in a fast manner. And third, we evaluate the performance of the proposed algorithm numerically and study how this affects the performance of a circuit switch. Our results show that Birkhoff+ is superior to previous algorithms in terms of throughput, running time, and number of switching configurations.

A hybrid optical/electrical datacenter network (HOE-DCN) integrates the benefits of electrical packet switching (EPS) and optical circuit switching (OCS) for better architectural scalability. Meanwhile, as each network service usually involves multiple virtual machines (VMs) that form a virtual network (VNT), how to reconfigure the VNTs in an HOE-DCN to adapt to the dynamic network environment becomes an interesting and important problem to tackle. In this work, we optimize the procedure of VNT reconfigurations that remap VNTs to given virtual network embedding (VNE) schemes, i.e. , scheduling the required VM migrations and optical cross-connect (OXC) reconfiguration properly such that the overall VNT reconfiguration latency can be minimized. We first assume that all the VM migrations should be scheduled before the OXC reconfiguration to minimize service interruptions, and formulate a mixed integer linear programming (MILP) model to solve the scheduling problem exactly. Then, with the same assumption, we propose a time-efficient heuristic to schedule parallel VM migrations in batches such that the bandwidth competition can be significantly relieved. Finally, we divide the OXC reconfiguration into several progressive steps, and design a joint scheduling algorithm to arrange VM migrations together with the OXC reconfiguration steps.

Nowadays, optical circuit switching is becoming an increasingly favored technology in scaling data center networks for its definitive advantages in data rate, power consumption, and device cost. Concurrently, reducing coflow completion time (CCT) is of great significance for improving application-level performance. However, minimizing CCT in circuit switched networks is totally different from that in traditional packet switched networks due to port constraints and circuit reconfiguration delays. To address this issue, this article proposes Grouped Optimization-based Scheduling (GOS), a CCT minimization algorithm for circuit switched networks integrating circuit and coflow scheduling. We first formalize the CCT minimization problem into a 0-1 programming problem, then relax and solve the problem in 2 steps to obtain the coflow order and flow grouping decisions on each circuit. Thus intra-group reconfiguration delays are saved, and small coflows can be prioritized at the group level. Theoretical analysis proves GOS is a 4-approximation algorithm in average CCT. To reduce computing overheads, we further propose a heuristic approximation algorithm. Extensive simulations show that the heuristic algorithm has satisfactory CCT performance (0.12× Varys, 0.36× Sunflow) as well as high throughput (16.74× Varys, 1.32× Sunflow), and well adapts to a wide range of reconfiguration delays and algorithm decision time.

Novel approaches to switching ultra-fast semiconductor optical amplifiers using artificial intelligence algorithms (particle swarm optimisation, ant colony optimisation, and a genetic algorithm) are developed and applied both in simulation and experiment. Effective off-on switching (settling) times of 542 ps are demonstrated with just 4.8% overshoot, achieving an order of magnitude improvement over previous attempts described in the literature and standard dampening techniques from control theory., This manuscript was accepted for publication in the IEEE/OSA Journal of Lightwave Technology on 21st June 2020. Open access code: https://github.com/cwfparsonson/soa_driving Open access data: https://doi.org/10.5522/04/12356696.v1

We introduce PULSE, a sub-microsecond optical circuit-switched data centre network architecture controlled by distributed hardware schedulers. PULSE is a flat architecture that uses parallel passive coupler-based broadcast and select networks. We employ a novel transceiver architecture, for dynamic wavelength-timeslot selection, to achieve a reconfiguration time down to O(100ps), establishing timeslots of O(10ns). A novel scheduling algorithm that has a clock period of 2.3ns performs multiple iterations to maximize throughput, wavelength usage and reduce latency, enhancing the overall performance. In order to scale, the single-hop PULSE architecture uses sub-networks that are disjoint by using multiple transceivers for each node in 64 node racks. At the reconfiguration circuit duration (epoch = 120 ns), the scheduling algorithm is shown to achieve up to 93% throughput and 100% wavelength usage of 64 wavelengths, incurring an average latency that ranges from 0.7-1.2 microseconds with best-case 0.4 microsecond median and 5 microsecond tail latency, limited by the timeslot (20 ns) and epoch size (120 ns). We show how the 4096-node PULSE architecture allows up to 260k optical channels to be re-used across sub-networks achieving a capacity of 25.6 Pbps with an energy consumption of 85 pJ/bit., 16 pages, 12 figures

As data centers enter the exascale computing era, the traffic exchanged between internal network nodes, increases exponentially. Optical networking is an attractive solution to deliver the high capacity, low latency, and scalable interconnection needed. Among other switching methods, packet switching is particularly interesting as it can be widely deployed in the network to handle rapidly-changing traffic of arbitrary size. Nanosecond-reconfigurable photonic integrated switch fabrics, built as multi-stage architectures such as the Clos network, are key enablers to scalable packet switching. However, the accompanying control plane needs to also operate on packet timescales. Designing a central scheduler, to control an optical packet switch in nanoseconds, presents a challenge especially as the switch size increases. To this end, we present a highly-parallel, modular scheduler design for Clos switches along with a proposed routing scheme to enable nanosecond scalable scheduling. We synthesize our scheduler as an application-specific integrated circuit (ASIC) and demonstrate scaling to a 256 × 256 size with an ultra-low scheduling delay of only 6.0 ns. In a cycle-accurate rack-scale network emulation, for this switch size, we show a minimum end-to-end latency of 30.8 ns and maintain nanosecond average latency up to 80% of input traffic load. We achieve zero packet loss and short-tailed packet latency distributions for all traffic loads and switch sizes. Our work is compared to state-of-the-art optical switches, in terms of scheduling delay, packet latency, and switch throughput.

Fast optical circuit switching has significant potential to solve scaling issues with traditional packet-switch-based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. Here we present a system-level integration of a nanosecond-scale $2\times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

This paper proposes and experimentally evaluates a fully developed novel architecture with purpose built low latency communication protocols for next generation disaggregated data centers (DDCs). In order to accommodate for capacity and latency needs of disaggregated IT elements (i.e., CPU, memory), this architecture makes use of a low latency and high-capacity circuit-switched optical network for interconnecting various end points that are equipped with multi-channel silicon photonic based integrated transceivers. In a move to further decrease the perceived latency between various disaggregated IT elements, this paper proposes a novel network topology that cuts down the latency over the optical network by 34% while enhancing system scalability and channel bonding over multi-core fiber (MCF) switched links to reduce head to tail latency and in turn increase sustained memory bandwidth for disaggregated remote memory. Furthermore, to reduce power consumption and enhance space efficiency, the integration of novel MCF-based transceivers, fibers, and optical switches are proposed and experimentally validated at the physical layer for this topology. It is shown that the integration of MCF-based subsystems in this topology can bring about an improvement in energy efficiency of the optical switching layer, which is above 60%. Finally, the performance of this proposed architecture and topology is evaluated experimentally at the application layer where the perceived memory throughput for accessing remote and local resources is measured and compared using electrical circuit and packet switching. The results also highlight a multi-fold increase in application perceived memory throughput over the proposed DDC topology by utilization and bonding of multiple optical channels to interconnect disaggregated IT elements that can be carried over MCF links.

Modular optical switch architectures combining wavelength routing based on arrayed waveguide grating (AWG) devices and multicasting based on star couplers hold promise for flexibly addressing the exponentially growing traffic demands in a cost- and power-efficient fashion. In a default switching scenario, an input port of the AWG is connected to an output port via a single wavelength. This can severely limit the capacity between broadcast domains, resulting in interdomain traffic switching bottlenecks. An unexplored solution to this issue is to exploit multiple AWG free spectral ranges (FSRs), i.e., to set up multiple parallel connections between each pair of broadcast domains. In this paper, we study, for the first time, the influence of the FSR count on the throughput of a multistage switching architecture and propose a generic and novel analytical framework to estimate the blocking probability. We assess the accuracy of our analytical results via Monte Carlo simulations. Our study points to significant improvements with a moderate increase in the number of FSRs. We show that an FSR count beyond four results in diminishing returns. Furthermore, to investigate the tradeoffs between the network- and physical-layer effects, we conduct a cross-layer analysis, taking into account pulse amplitude modulation and rate-adaptive forward error correction. We illustrate how the effective bit rate per port increases with an increase in the number of FSRs.

There are more and more structured traffic flows (a.k.a coflow) in today's data center networks. Completing a coflow is extremely important for various applications, e.g., MapReduce. To reduce the coflow completion time or CCT, one may increase the link capacity by applying advanced optical circuit switches in data center networks. Due to special features of optical circuit switches, both traffic scheduling and circuit scheduling will influence the CCT. However, previous solutions have some significant limitations: they consider either coflow scheduling, or circuit scheduling for only one optical circuit switch, which are both insufficient. In this paper, we study the integrated coflow and circuit scheduling (GCCS) problem with the objective to minimize the CCT, and prove its NP-hardness. We present an integrated algorithm which includes two steps, coflow scheduling and circuit scheduling, respectively. We also analyze that the proposed algorithm can achieve the approximation ratio $O(h)$O(h) in most practical situations, where $h$h is the maximum number of ports among all lightpaths. Through large-scale simulations, we demonstrate that the integrated solution can significantly reduce the CCT by about 43-70 percent compared with the state-of-the-art coflow scheduler for optical networks.

All optical or hybrid electrical/optical switching data center network (DCN) architectures are capable of adapting the optical-layer topology to various network traffic demands based on the flexibility of optical switching technology. The topology reconfiguration strategies in previous research simply attempt to reconfigure optical circuit switching (OCS) links to offload heavier rack-to-rack traffic. However, due to the complex multi-layer interconnections and the various network traffic patterns in DCNs, the OCS links will not only offload the network traffic between its source and destination racks, but also forward the network traffic that belongs to the adjacent racks of the source and destinations racks. Previous strategies ignore the forwarding traffic and result in sub-optimal solutions. In order to overcome the shortcomings of previous methods and make full use of the OCS link resources in DCNs, an effective topology reconfiguration strategy named optical circuit bridge (OCBridge) has been proposed in our recent work. The main idea of our OCBridge is to take into account the traffic demands between the source and destination regions of each OCS link. In this paper, we first review our OCBridge, and then in simulation, we evaluate the performance of our OCBridge by testing it in two typical OCS-based DCNs, including OpenScale and Helios. Under our OCBridge, we analyze the outstanding network throughput performance of the DCNs and investigate the communication distance of traffic demands. Finally, in experiment, we deploy our OCBridge to a small prototype of OpenScale and verify that our OCBridge is capable of accelerating the distributed computing applications compared with previous topology reconfiguration strategies.

High-performance systems are increasingly bottlenecked by the growing energy and communications costs of interconnecting numerous compute and memory resources. Recent advances in integrated silicon photonics offer the opportunity of embedding optical connectivity that directly delivers high off-chip communication bandwidth densities with low power consumption. This paper reviews the design and integration of silicon photonic interconnection networks that address the data-movement challenges in high-performance systems. Beyond alleviating the bandwidth/energy bottlenecks, embedded photonics can enable new disaggregated architectures that leverage the distance independence of optical transmission. This review paper presents some of the key interconnect requirements to create a new generation of photonic architectures for extreme scale systems, including aggregate bandwidth, bandwidth density, energy efficiency, and network resources utilization.

With the rapid growth in intra-datacenter traffic, the high power consumption stemming from the huge number of electrical switches is becoming a critical issue. Hence, high-port-count optical circuit switches are urgently needed. In this paper, we overview recently developed optical circuit switch architecture based on two-dimensional switches, i.e., space switches and wavelength-routing switches. The attainable maximum switch port counts and hardware requirements are quantitatively evaluated through extensive computer simulations that consider 10-Gbps intensity modulation with direct detection systems, 43-Gbps differential quadrature phase-shift keying with self-coherent detection systems, and 128-Gbps dual-polarization quadrature phase-shift keying with coherent detection systems. The simulation results confirm the existence of switching architecture that can accommodate more than 1,000 ports with relatively light hardware requirements.

Circuit switching is a de facto switching technology widely employed in today's networks where the conventional approaches to routing have remained unchanged for many years. This paper develops a new and very different methodology, by incorporating a supervised naive Bayes (NB) classifier, to assist least loaded (LL) routing and to further improve its performance that has remained the best among all the routing approach for the past several decades. Specifically, by iteratively learning the information of historical network snapshots, the NB classifier predicts potential future circuit blocking probability between each node pair if a service connection is established via a certain route between the node pair. The snapshots are taken for each service request arriving at an operating network that keeps on accepting and releasing dynamic service connections and records the number of busy capacity units on each link at each snapshot instance. The candidate route for serving a new request is selected based on both link loads and the potential future blocking probability in the entire network in case that this route is indeed used. The performance of the proposed approach is studied via simulations and compared with the conventional LL algorithm. The results indicate that the supervised NB classifier-assisted LL routing algorithm effectively reduces the blocking probability of service connections and outperforms the conventional LL routing algorithm. To speed up the learning process (which is based on a large number of network snapshots), we also develop a framework to incorporate the proposed approach in a parallel learning system. A network control system supporting online NB classifier-assisted LL routing algorithm is also described.

This paper presents a new concept and approach for topology control and switching in distribution systems by extending the traditional circuit switching to laterals and single-phase loads. Voltage unbalance and other key performance indicators including voltage magnitudes, line loading, and energy losses are used to characterize and demonstrate the technical value of opti- mizing system topology on a per-phase basis in response to feeder conditions. The near-optimal per-phase topology control is defined as a series of hierarchical optimization problems. The proposed approach is applied to IEEE 13-bus and 123-bus test systems for demonstration, which included the impact of integrating electric vehicles (EVs) in the test circuit. It is concluded that the proposed approach can be effectively leveraged to improve voltage profiles with electric vehicles, the extent of which depends on the perfor- mance of the base case without EVs.

Contemporary optical circuit switch (OCS) scheduling techniques are still struggling to balance the tradeoff between scheduling efficiency and computational run time. To diminish this gap, we introduce Lumos —a fast and efficient OCS scheduling technique. Lumos negotiates the tradeoff between the cost of prolonging the current configuration and the time penalty of circuit reconfigurations. An extensive evaluation shows that Lumos matches the state of the art in scheduling efficiency while running orders of magnitude faster.

We present a large-scale optical circuit switch architecture using wavelength-tunable and bandwidth-variable silicon photonic filters. The attainable switch port count is quantitatively evaluated through extensive computer simulations. The requirements for constructing a 1, $024\times1$ ,024 optical circuit switch are analyzed on 10-, 28-, and 56-Gb/s signals. The simulation results are verified through transmission experiments.

Nowadays chip multiprocessors (CMPs) tend to increase the number of cores, usually implementing a distributed shared last level cache (LLC). The network on chip (NoC) is in charge of interconnecting the cores, memory controller(s) and cache banks, largely impacting memory access latency. Packet switching (PS) is typically used in NoCs but circuit switching (CS) may complement PS achieving higher performance if the circuit is established before its need. In this paper we propose PROSA, an architecture to improve memory access latency by using CS. In PROSA, the coherence protocol steers the circuit setup logic in order to configure circuits before they are needed and only for the time they are required. PROSA uses a clustered router approach where groups of four routers are clustered and their circuit control logic is combined. Based on key design decisions, we present different PROSA versions, analyzing their impact on applications and NoC performance. PROSA is able to reduce applications’ execution time by 35 percent while it significantly reduces average network flit latency by 54 percent, leading to a reduction of miss load (and store) latency of 21 percent (in CMP systems with 64 processors). PROSA needs 8.4 percent more area, but reduces power consumption by 7 percent.

Continuous development of Network-on-Chip (NoC) enables different types of applications to run efficiently in a Multiprocessor System-on-Chip (MP-SoC). Guaranteed service (GS) can be provided by circuit switching NoC and Best effort service (BES) can be provided by packet switching NoC. A hybrid NoC containing both packet and circuit switching, can provide both types of services to these different applications. But these different applications can be of different security levels and one application can interfere another application’s timing characteristics during network transmission. Using this interference, a malicious application can extract secret information from higher security level flows (timing side channel) or two applications can communicate covertly violating the system’s security policy (covert timing channel). We propose different mechanisms to protect hybrid routers from timing channel attacks. For design space exploration, we propose three timing channel secure hybrid routers viz. Separate Hybrid (SH), Combined with Separate interface Hybrid (CSH), and Combined Hybrid (CH) routers. Simulation results show that all three routers are secure from timing channel when compared to a conventional hybrid router. Synthesis results show that the area increments compared to a conventional hybrid router are only 7.63, 11.8, and 19.69 percent for SH, CSH, and CH routers respectively. Thus simulation and synthesis results prove the effectiveness of our proposed mechanisms with acceptable area overheads.

Applying optical switching to data center networks can greatly expand network bandwidth and reduce electrical power consumption, both of which are needed to meet the explosive traffic increase. The optical switch offers large bandwidth switching capability, and so eliminates the multistage switch network architecture needed with electrical switching. Furthermore, the single stage architecture of the optical switch greatly simplifies operating costs, which include cabling, while substantially reducing the number of transponders needed. Data center networks place very different demands on optical systems than communication networks. Grasping the right direction to proceed is of paramount importance. To realize the full potential of optical switches, such as scalability and cost effectiveness, we analyze the role of large-scale optical circuit switches and discuss the realization technologies that combine the two dimensions of space and wavelength. Our recent advances in large port-count optical switches are presented.

We analyze the scalability of electro-optic Mach–Zehnder-based silicon photonic switch networks. We describe a simulation framework based on the transfer matrix method that enable to model any type of multistage networks. We simulate three common network topologies – Benes, path-independent loss, and double-layer – and analyze their scalability by performing optical link numerical simulations for 50 Gbps non-return-to-zero signals. Our study shows that for a radix-16, the double-layer network performs better with a link power penalty smaller than 1 dB thanks to its dilated arrangement. For equivalent radix, the Benes and path-independent loss networks have link power penalties larger than 4 dB. Our simulations also show stringent requirements for the waveguide crossing crosstalk, whose value should be smaller than −35 dB to close any realistic link budget.

While preparing a modern data center for startup, the commissioning process involved primary circuit switching that resulted in two voltage transformer (VT) failures. As a result, we conducted a comprehensive investigation of the VT failures. As the investigation proceeded, VT ferroresonance on circuit opening and high-frequency switching transients on closing emerged as possible root causes of the failures. After incorporating extensive transient simulations and three rounds of field transient measurements, we designed and implemented a complete solution that included the sizing of snubbers to overcome excessive switching transients and the development of a saturable reactor to protect VTs against the effects of ferroresonance. This article describes the root causes, simulations, field measurements, recommended solutions, and solution implementation for this event. The correlation between field measurements and simulation results shows the effectiveness of modeling the implemented solutions.

In spite of escalating thermal challenges imposed by high power consumption, most reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are unable to tackle the thermal management issues directly at the architectural level. Rather, to avoid chip being overheated, tasks running in a “hot” node have to be migrated to a “cooler” one, resulting in increased distance between communicating nodes and ultimately poor performance. In this paper, we propose a new 3D NoC architecture that genuinely supports runtime thermal-aware task management. Dubbed Hierarchical Ring Cluster (HRC), this new hierarchical 3D NoC architecture has three levels across its entire network hierarchy: 1) nodes are grouped as rings, 2) rings are then grouped into cubes, and 3) multiple cubes are connected to form the whole network. Routing in a HRC system is also performed in a hierarchical manner: Paths are set up within rings using low latency circuit switching, and data that need to cross the rings or cubes are routed following dimension-order routing supported by wormhole switching. In this organization, “hot” tasks that need to migrate can move along the rings without incurring increased communication distances. Our experimental results have confirmed that the proposed HRC architecture has a much lower network latency than other known 3D NoC architectures. When working with runtime thermal-aware task migration approaches, HRC can help reduce latency by as much as 80 percent compared to thermal-aware task migration approaches applied to 3D mesh NoC topologies.

To accomplish high-bandwidth and low-latency communications among tens or even hundreds of nodes with low power consumption, dual radial and angular grating optical network (DRAGON), a new integrated high-radix strictly nonblocking optical switching fabric, is proposed in this paper. The topology and routing algorithms of DRAGON are discussed, and a formal proof for the strictly nonblocking property is presented. With the loss model developed, we show DRAGON has significantly lower worst-case loss as well as average loss compared with other widely studied integrated nonblocking switching fabrics. In addition, our crosstalk analysis also suggests a lower crosstalk of DRAGON. For example, for 32 wavelength division multiplexing channels, both the worst-case loss and average loss of ${\text{180}}\times {\text{180}}$ DRAGON are around 20 dB lower than crossbar of the same size, and 28 dB lower than ${\text{128}}\times {\text{128}}$ Benes. Furthermore, due to the strictly nonblocking property, DRAGON has advantages of smaller communication latency and larger throughput compared with Benes switching fabric.

The circuit switched optical network on chip (ONoC) is popularly employed since the optical buffer is not available. However, this technique suffers from limited transmission bandwidth, high setup-time overhead, and high network resource contention, which consequentially induces long latency and degraded throughput. In this paper, we propose a new ONoC architecture aiming at ultralow setup cost, improved scalability, and contention-free communication. We first utilize wavelength division multiplexing (WDM) to introduce the basic version of this ONoC with efficient wavelength assignment. A series of potential versions are developed by using multiple waveguides to relieve the pressure on the number of wavelengths. These potential versions can make a tradeoff between required wavelengths and waveguides and improve the scalability. The new architectures employ two layers relying on the interlayer coupler, which contributes to the decrease of crossing losses. The simulation results show that the architecture can achieve 133% saturated bandwidth improvement compared with the traditional mesh ONoC employing WDM technology under the uniform traffic pattern.

Optical circuit switching may be instrumental in meeting the cost, energy, and aggregate bandwidth requirements of future data center networks. However, conventional MEMS beam-steering cross-connects cannot provide submillisecond switching with the port count necessary for data centers. Here, we investigate a novel noncrossbar selector switch architecture and pupil-division switching layout to improve optical switching performance by relaxing the requirement of arbitrary switch configurability. This architecture and switch design enable MEMS beam-steering micromirrors to scale to microsecond response speeds while supporting high port count and low loss switching, and can realize a number of useful interconnection topologies. We present the design, fabrication, and experimental characterization of a proof-of-principle prototype using a single comb-driven MEMS mirror to achieve 150 μs switching of 61 ports between four preprogrammed interconnection mappings. We demonstrate the scalability of this switch architecture with a detailed optical design of a 2048-port selector switch with 20 μs switching time.

Scaling the capacity while maintaining low latency and power consumption is a challenge for hierarchical data center networks (DCNs) based on electrical switches. In this work we present a novel all-optical flat DCN architecture OPSquare that potentially addresses the scaling issues by employing parallel intra-/inter-cluster switching networks, distributed fast WDM optical cross-connect (OXC) switches, and a novel top-of-rack (ToR) switch architecture. The fast (nanoseconds) WDM OXC switches allow flexible switching capability in both wavelength and time domains and statistical multiplexing. The OPSquare DCN performance targeting Petabit/s capacity has been thoroughly assessed. First the packet loss, latency, throughput, and scalability are numerically investigated under realistic data center traffic model. Results indicate that when scaling the DCN size up to 1024 ToR switches, a packet loss ratio below 10-6 and a server end-to-end latency lower than 2 μs can be guaranteed at load of 0.3 with limited 20 kB buffer. Then, the experimental evaluation of the DCN by employing 4 × 4 OXC prototypes shows multi-path dynamic switching with flow control operation. The case deploying 32 × 32 and 64 × 64 OXC switches connecting 1024 and 4096 ToRs are emulated and limited performance degradation has been observed. The potential of switching higher-order modulation and waveband signals further proves the suitability of OPSquare architecture for Petabit/s and low-latency DCN by using optical switches with moderate radix.

Scheduling algorithms are crucial for most existing switches to improve the throughput. However, the delay of the switching fabric cannot be guaranteed with such scheduling algorithms. This paper aims to design a novel load-balanced wire-speed multicast switching fabric along with the attractive merits of network coding. We adopt a two-phase self-routing switching fabric constructed by Boolean-multicast concentrators (SRBMCs), where the first SRBMC distributes the incoming cells to its outputs uniformly and the second allows the distributed cells to be self-routed and multicast to their destinations concurrently. To further improve the switching performance, linear network coding is smoothly combined with SRBMC to reduce the packet loss rate. Theoretical analysis and numerical simulation demonstrate that the proposed switching fabric cannot only achieve wire-speed multicast switching but also be recursively constructed into an indefinite large-scale one with such merits as no internal buffers, low complexity, and guarantee in switching delay. Finally, we implement the proposed fabric on Field-Programmable Gate Array and verify its performance in multicast switching.

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA—a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short request packets, and benefits from circuit switching for longer, delay sensitive response packets. While a request is being served by the LLC, CIMA attempts to set up a circuit for the corresponding response packet. By the time the request packet is served and the response gets ready, a circuit has already been prepared, and as a result, the response packet experiences short delay in the network. A detailed evaluation targeting a 64-core CMP running scale-out workloads reveals that CIMA improves system performance by 21 percent over the state-of-the-art hybrid circuit-packet-switched network.

This paper reports on a novel ring-based data center architecture composed of multidimensional switching nodes. The nodes are interconnected with multicore fibers and can provide switching in three different physical, hierarchically overlaid dimensions (space, wavelength, and time). The proposed architecture allows for scaling in different dimensions while at the same time providing support for connections with different granularity. The ring topology reduces the number of different physical links required, leading to simplified cabling and easier link management, while optical bypass holds the prospect of low latency and low-power consumption. The performance of the multidimensional switching nodes has been investigated in an experimental demonstration comprising three network nodes connected with multicore fibers. Both high capacity wavelength connections and time-shared subwavelength connections have been established for connecting different nodes by switching in different physical dimensions. Error-free performance ( $\text{BER} ) has been achieved for all the connections with various granularity in all the investigated switching scenarios. The scalability of the system has been studied by increasing the transmission capacity to 1 Tbit/s/core equivalent to 7 Tbit/s total throughput in a single seven-core multicore fiber. The error-free performance ( $\text{BER} ) for all the connections confirms that the proposed architecture can meet the existing demands in data centers and accommodate the future traffic growth.

Optical integrated network (OIN) is a promising alternative to overcome the restrictions that electrical networks-on-chip (eNoCs) will face in the next generation of multiprocessor integrated systems due to electrical interconnects’ physical limitations. OINs present a higher bandwidth and lower power consumption but their full capabilities are curbed by high latency controllers. Control techniques, such as circuit switching, impose a high latency to perform the correct network routing and a better solution must be found in order to fully utilize OINs. In this letter, we have designed and modeled a low-latency centralized controller (LUCC). For validation purposes, we modeled different Mach–Zehnder interferometer (MZI)-based optical interconnects that employ the proposed LUCC. We obtain a response time of only one clock cycle when using the LUCC, even when conflicts are found.

Optical circuit switches with fast switching times can provide rapidly reconfigurable bandwidth in data center networks. Silicon photonic switches are attractive candidates with their fast response times and CMOS process compatibility. In this paper, we report on a 50 x 50 silicon photonic switch with MEMS-actuated vertical adiabatic couplers. The switch is monolithically integrated on a 7.6 x 7.6 mm(2) chip. It has an on-chip insertion loss of 8.5 dB. Our switch exhibits a sub-microsecond switching time (0.85 mu s), a broad spectral bandwidth (1400-1700 nm), and digital switching characteristic. The switch architecture is highly scalable as light passes through only one switching element irrespective of the switch size.

Networks-on-chips (NoCs) are an increasingly popular communication infrastructure in single chip VLSI design for enhancing parallelism and system scalability. Processing elements (PEs) connect to a communication topology via NoC switches, which are responsible for runtime establishment and management of inter-PE communication channels. Since NoC switch design directly affects overall system performance and exploited communication parallelism, much previous work focused on efficient NoC switch design. In this paper, we present MACS—a highly parametric NoC switch architecture that provides reduced data transfer latency, increased designer flexibility, and scalability as compared to previous architectures by combining and enhancing several NoC design strategies. MACS enhances inter-PE communication using a circuit switching technique with minimal adaptive routing and a simple and fair path resolution algorithm to maximize bandwidth utilization. We evaluate area and performance of an FPGA implementation of MACS, and, show that compared to previous work, MACS offers a 2x to 7x decrease in average channel setup latency, a 1.7x to 2x reduction in area requirements, similar average packet latency, up to a 6x increase in the network saturation point, and up to a 1.4x increase in bandwidth utilization. Additionally, we illustrate MACS’s low average channel setup latency using six network traffic patterns and eight parallel JPEG decompression core trace simulations.

Transparent optical circuit switching can improve the aggregate bandwidth, scalability, and cost of data center networks provided, it can meet the performance requirements on switching speed, port count, and optical efficiency. Here, we examine the theoretical scaling limits of transparent nonblocking optical switches based on MEMS electrostatic tilt mirror devices. Using physical optics and electromechanics, we present a first principles analysis of how the response speeds of a set of canonical devices scale as a function of switch port count, crosstalk, and insertion loss. Our model indicates that the optimal actuator design (parallel plate versus vertically offset comb) and actuation method (digital versus analog) changes as a function of switch port count. It also suggests that conventional switch topologies do not allow a favorable tradeoff between switching speed and optical efficiency or crosstalk. However, high switching speeds can be achieved by multistage switch architectures such as the two examples we describe, a multiport wavelength switch and a wavelength-independent space switch.

With the significant increase in the number of processing elements in NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and quality-of-service (QoS) guarantees. The main gap observed in the NoC-based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system user must statically define, for example, the scheduling policy, communication priorities, and the communication switching mode of applications. The goal of this paper is to investigate the runtime adaptation of the NoC resources, according to the QoS requirements of each application running in the MPSoC. This paper adopts an NoC architecture with duplicated physical channels, adaptive routing, support to flow priorities and simultaneous packet and circuit switching. The monitoring and adaptation management is performed at the operating system level, ensuring QoS to the monitored applications. The QoS acts in the flow priority and the switching mode. Monitoring and QoS adaptation were implemented in software, resulting in flexibility to apply the techniques to other platforms or include other adaptive techniques, as task migration or DVFS. Applications with latency and throughput deadlines run concurrently with best-effort applications. Results with synthetic and real application reduced in average 60% the latency violations, ensuring smaller jitter and throughput. The execution time of applications is not penalized applying the proposed QoS adaptation methods.

This letter aims at optimizing the mapping of embedded applications on the hybrid network-on-chip (NoC) that intermingles multiple switching mechanisms. Specifically, we identify the critical characteristics of those switching mechanisms, deriving a new latency and energy model for this type of networks. A novel mapping scheme based on a branch-and-bound algorithm is proposed to map cores onto the NoC and allocate communications to different switching mechanisms simultaneously, such that the average communication latency and energy are optimized. A set of embedded applications are exploited for evaluation. Experimental results show that, compared with three existing mapping strategies, our mapping scheme can obtain considerable reductions in communication latency and energy on the hybrid NoC.

This paper reports all-optical, function programmable, transparent, intra- and inter-data center networking (DCN) using space and time-division multiplexing (SDM/TDM) within data centers and wavelength division multiplexing (WDM) between data centers. A multielement fiber is used for SDM transmission to provide a large quantity of optical links between the top-of-racks (ToRs) and the function programmable cluster switch. Beam-steering large-port-count fiber switches, used as central cluster switches and intercluster switch, provide a single hop optical circuit switching solution, and also enable network function programmability for DCN to support variable traffic patterns and different network functions. A TDM switch as a plug-in function provides intra-cluster communication with variable capacity and low latency. The flat-structured intra data center architecture, with a circuit-switched SDM and TDM hybrid network enables scalable, large-capacity and low-latency DCN communication. In addition, all-optical ToR-to-ToR inter-DCN is realized through metro/core networks. A highly-nonlinear fiber based all-optical SDM-to-WDM converter transfers three SDM signals to three-carrier spectral superchannel signals, which are transmitted to the destination DCN, through the metro/core networks. The all-optical ToR-ToR cross-DCN connections enable the geographically distributed DCNs to appear as one big data center.

A multidomain optical transport network composed of heterogeneous optical transport technologies (e.g., flexi/fixed-grid optical circuit switching and optical packet switching) and control plane technologies (e.g., centralized OpenFlow or distributed GMPLS) does not naturally interoperate, and a network orchestration mechanism is required. A network orchestrator allows the composition of end-to-end network service provisioning across multidomain optical networks comprising different transport and control plane technologies. Software-defined networking (SDN) is a key technology to address this requirement, since the separation of control and data planes makes the SDN a suitable candidate for end-to-end provisioning service orchestration across multiple domains with heterogeneous control and transport technologies. This paper presents two different network orchestration's architectures based on the application-based network operations (ABNO) which is being defined by IETF based on standard building blocks. Then, we experimentally assesses in the international testbed of the STRAUSS project, an ABNO-based network orchestrator for end-to-end multi-layer (OPS and Flexi-grid OCS) and multidomain provisioning across heterogeneous control domains (SDN/OpenFlow and GMPLS/Stateful PCE) employing dynamic domain abstraction based on virtual node aggregation.

This paper presents and experimentally demonstrates the generalized architecture of Openflow-controlled optical packet switching (OPS) network. Openflow control is enabled by introducing the Openflow/OPS agent into the OPS network, which realizes the Openflow protocol translation and message exchange between the Openflow control plane and the underlying OPS nodes. With software-defined networking (SDN) and Openflow technique, the complex control functions of the conventional OPS network can be offloaded into a centralized and flexible control plane, while promoted control and operations can be provided due to centralized coordination of network resources. Furthermore, a contention-aware routing/rerouting strategy as well as a fast network adjustment mechanism is proposed and demonstrated for the first time as advanced Openflow control to route traffic and handle the network dynamics. With centralized SDN/Openflow control, the OPS network has the potential to have better resource utilization and enhanced network resilience at lower cost and less node complexity. Our work will accelerate the development of both OPS and SDN evolution.

Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many-core systems. This paper proposes a hybrid scheme for NoCs, which aims at obtaining low latency and low power consumption. In the presented hybrid scheme, a novel switching mechanism, called virtual circuit switching, is proposed to intermingle with circuit switching and packet switching. Flits traveling in virtual circuit switching can traverse the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are allowed to share a common physical channel. Moreover, a path allocation algorithm is proposed in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized. A set of synthetic and real traffic workloads are exploited to evaluate the effectiveness of the proposed hybrid scheme. The experimental results show that our proposed hybrid scheme can efficiently reduce the communication latency and power. For instance, for real traffic workloads, an average of 20.3% latency reduction and 33.2% power saving can be obtained when compared with the baseline NoC. Moreover, when compared with the NoC with virtual point-to-point connections (VIP), the proposed hybrid scheme can reduce the latency by 6.8% with the power decreasing by 11.3% averagely.

We review our work on an intra-data center (DC) network based on co-deployment of optical packet switching (OPS) and optical circuit switching (OCS), conducted within the framework of a five-year-long national R&D program in Japan (∼March 2016). For the starter, preceding works relevant to optical switching technologies in intra-DC networks are briefly reviewed. Next, we present the architecture of our torus-topology OPS and agile OCS intra-DC network, together with a new flow management concept, where instantaneous optical path on-demand, so-called Express Path is established. Then, our hybrid optoelectronic packet router (HOPR), which handles 100 Gbps (25 Gbps × 4-wavelength) optical packets and its enabling device and sub-system technologies are presented. The HOPR aims at a high energy-efficiency of 0.09 [W/Gbps] and low-latency of 100 ns regime. Next, we provide the contention resolution strategies in the OPS and agile OCS network and present the performance analysis with the simulation results. It is followed by the discussions on the power consumption of intra-DC networks. We compare the power consumption and the throughput of a conventional fat-tree topology with the N -dimensional torus topology. Finally, for further power saving, we propose a new scheme, which shuts off HOPR buffers according to the server operation status.

Optical network-on-chip (ONoC) is a promising solution for its high bandwidth and low energy consumption. However, optical circuit switching requires an electrical control network, which leads to network congestion, low network utilization, high latency, and an overhead in energy consumption. In this letter, we propose an architecture called RPNoC based on ring topology using packet switching. A wavelength assignment method and a deadlock-free deterministic routing algorithm are jointly designed, which significantly reduce the maximum number of hops using much fewer optical devices compared with other packet-switched ONoCs. The simulation is carried out for 64-node RPNoC under uniform and realistic traffic pattern. The evaluation results show that it yields higher throughput, lower latency, and lower energy consumption than mesh and ring networks.

We discuss silicon photonic switch fabric designs that target data-intensive computing networks, reviewing recent results, and projecting future performance goals. We analyze the achievements of demonstrated hardware in terms of switching time, footprint, crosstalk, and power consumption, concluding that the most crucial metric to improve upon is net loss. We propose integrating semiconductor optical amplifiers into the switch fabric using either flip-chip or wafer-bonding technology, and investigate its potential merits alongside several challenges in implementation. Furthermore, we explore the dominant causes of crosstalk, and discuss manners for reducing it. We perform switch simulations that project a 7-dB reduction in crosstalk, when using a push–pull, rather than a single-ended phase shifter drive scheme. We also evaluate crosstalk effects on transmission performance using a full-link model that incorporates multiple crosstalk-accumulating photonic switch hops. The study demonstrates the degree to which crosstalk may degrade signal integrity after just a few occurrences. Finally, a comparison of four topologies highlights tradeoffs in physical-layer design and scheduling complexity, illustrating the scales that may be accomplished with the simplest topologies, and the device improvements required to achieve the more robust architectures.

This paper presents a network model based on a NGN architecture applied to the Mexican rural context and deployed over the optical fiber backbone of the e-Mexico (now Mexico Conectado) system. The proposed model considers the integration of access networks for GERAN, UTRAN and E-UTRAN users, allowing also the interconnection with circuit switched networks. We use the E model proposed by ITU-T to maintain a minimum level of voice quality R>70. Additionally, we calculate the estimated bandwidth consumption during the seven phases that SIP requires establishing a telephone call on IMS networks. Our model includes the calculation of the most significant NGN parameters, taking into account the use of an optimal codec, a percentage of packet loss and link utilization level, for the conditions of the Mexican rural environment and the e-Mexico (now Mexico Conectado) system infrastructure.

Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budget from communication toward computation. As core counts scale into the 100s, on-chip interconnect fabrics must support increasing heterogeneity and voltage/clock domains. Synchronous NoCs require either a single clock distributed globally or clock-crossing data FIFOs between clock domains [1]. A global clock requires costly full-chip margining and significant power and area for clock distribution, while synchronizing data FIFOs add power, performance, and area overhead per clock crossing. Source-synchronous NoCs mitigate these penalties by forwarding a local clock along with each packet, but still suffer from high data storage power due to packet switching. Circuit switching removes intra-route data storage, but suffers from low network utilization due to serialized channel setup and data transfer [2]. Hybrid packet/circuit switching parallelizes these operations for higher network utilization. A 16×16 mesh, 112b data, 256 voltage/clock domain NoC with source-synchronous operation, hybrid packet/circuit-switched flow control, and ultra-low-voltage optimizations is fabricated in 22nm tri-gate CMOS [3] to enable: i) 20.2Tb/s total throughput at 0.9V, 25°C, ii) a 2.7× increase in bisection bandwidth to 2.8Tb/s and 93% reduction in circuit-switched latency at 407ps/hop through source-synchronous operation, iii) a 62% latency improvement and 55% increase in energy efficiency to 7.0Tb/s/W through circuit switching, iv) a peak energy efficiency of 18.3Tb/s/W for near-threshold operation at 430mV, 25°C, and v) ultra-low-voltage operation down to 340mV with router power scaling to 363μW.

Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.

An optical packet and circuit integrated network (OPCInet) provides both high-speed, inexpensive services and deterministic-delay, low-data-loss services according to the users’ usage scenarios, from the viewpoint of end users. From the viewpoint of network service providers, this network provides large switching capacity with low energy consumption, high flexibility, and efficient resource utilization with a simple control mechanism. This paper presents the recent progress made in the development of OPCInet and its extension to software-defined networking (SDN). We have developed OPCI nodes, which are capable of layer 3 switching from/to an Ethernet frame to/from an optical packet in the optical packet edge part and a burst-tolerant optical amplifier and an optical buffer with optical fiber delays in 100 Gbps optical packet switching part. The OPCI node achieves a packet error rate less than $10^{-4}$ and is used as a node in a lab-network that has access to the Internet. A distributed automatic control works in a control plane for the circuit switching part and in a moving boundary control between optical packet resources and circuit resources. Our optical system for packet and circuit switching works with a centralized control mechanism as well as a distributed control mechanism. We have shown a packet-based SDN system that configures mapping between IP addresses and OPCI node identifiers and switching tables according to the requests from multiple service providers via a web interface.

The explosion of Internet traffic calls for quality of service (QoS)-guaranteed packet transmission in wavelength division multiplexing (WDM) networks with high energy and bandwidth efficiency. Conventional routing and wavelength assignment (RWA) algorithms focus on circuit switching, which does not well meet this requirement due to the bursty nature of IP traffic. Based on a novel traffic matrix decomposition technique, we study the joint design of traffic scheduling and routing in a reconfigurable WDM optical network to improve energy and bandwidth efficiency. Specifically, every node in the network is equipped with a set of parallel tunable lasers, each with a reconfiguration overhead. A dynamic matrix is adopted to model the traffic among the nodes and is decomposed into a set of transmission configurations (i.e., traffic scheduling). The configurations are then fulfilled by tuning the parallel lasers and routing the scheduled traffic under the topology constraint, to achieve loss-free packet transmissions with bounded delay (i.e., QoS guarantee). We reveal that a tradeoff exists between the packet delay and the required number of tunable lasers. The latter is then minimized under a given packet delay to save energy. As far as we know, this is the first work to adopt traffic matrix decomposition in WDM networks to save energy. The proposed framework is validated by extensive simulation studies.

A dual price-based congestion control (DPCC) mechanism for optical burst switching (OBS) networks is proposed in this paper, which can achieve an optimal rate-reliability tradeoff by allocating proper network traffic and resources based on the idea of network utility maximization (NUM). The DPCC uses the congestion and reliability prices and feedback information to dynamically adjust the users’ data sending rate and the end-to-end data transmission reliability in an OBS network. The performance of DPCC is evaluated and analyzed through simulations. Results verify that DPCC works very well in terms of its convergence and optimality. Moreover, compared with TCP, DPCC can achieve a maximum network utility, a parameter which can be used to reflect the overall user satisfaction degree in a network. DPCC is scalable due to its distributed nature.