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This paper presents the elimination of common mode (CM) conducted emissions in three-phase four-wire four-pole inverters connected to an AC distribution bus and operating in grid-following mode. Two novel control strategies are proposed and compared to the CM emission limits in the military standard 461G. Delta modulation and model predictive control both demonstrate elimination of the common mode voltage at the output of the three-phase four-pole inverter and the ability to meet the military standard’s requirements without a CM choke. The differential mode performance is comparable to that of three-dimensional space vector modulation, which does not cancel CM emissions. A physics-based model of the system was developed using state space equations to simulate the conducted emissions that can be expected with the two proposed methods. As the proposed methods result in increased switching frequency, wide bandgap devices were used to build a laboratory prototype, which successfully validate the simulated results.

A switching state selection scheme for a five level stacked multilevel inverter for open end winding motor drive is presented in this work. Using the proposed scheme, converter can be operated with a single DC supply and with zero common mode voltage. In addition, the switching transition of high voltage switches occurs at zero voltage conditions. The degree of freedom provided by the redundant switching states and voltage vectors of the inverter topology is utilised to design the modulation scheme. The proposed switching state selection leads to inherent capacitor balancing without using any extra sensors and fundamental frequency switching of the high voltage switches of the topology. The modulation scheme uses triangular carrier comparison and hence avoids the complexity of sub-sector identification and dwell time calculation. Half wave symmetry in output waveforms is ensured by maintaining synchronous sampling with constant samples per fundamental cycle. The inverter topology and the effectiveness of state selection scheme is experimentally validated on an open end winding induction motor drive and experimental results showing steady state and dynamic operation are presented.

In this paper, a new method is introduced for operation of three-phase symmetric cascaded H-bridge (CHB) multilevel inverter (MLI) after failure of power switches. When a switch fails, the faulty leg of the H-bridge is bypassed and the remaining leg is kept in use. Even with multiple faults in different H-bridge cells, the CHB is optimally reconfigured to continue its operation with its maximum healthy capacity. Based on the remaining operational part of the converter, a fault tolerant control scheme with zero-sequence voltage injection (ZSVI) is proposed to synthesize a balanced line-to-line voltage. Using this method, the post-fault line-to-line voltage of CHB is maximized with the minimum common mode voltage (CMV). Reduction of CMV is of importance in motor drive application. Also, fundamental component of CMV affects the real power of CHB phase legs. Through reducing the fundamental CMV, unidirectional power transfer from the dc side to the ac load is achieved in a wide operation region. The performance of the presented fault tolerant technique is verified in MATLAB/SIMULINK environment and validated on a three-phase 5-level hardware prototype

To balance the phase output currents of a multi- phase inverter, negatively coupled inductors (NCIs) can be used to achieve a larger differential mode (DM) loop impedance than the common mode (CM) loop impedance. For a good current sharing effect, the inductances of the NCIs should be large, leading to bulky size and cost ineffectiveness, which should be avoided in high-power applications. This paper proposes a novel current balancing method based on parallel resonance. A parallel resonant network (PRN) is inserted between any two phases. With -Y transform, the inductor common point and the capacitor common point are generated, either of which can be used as the CM output node. For a series-series compensated wireless power transfer system, part of the existing compensating capacitance can be employed to form PRNs with the added paralleling inductors. The DM currents are suppressed by the large impedance of the PRNs. Compared with the existing method, the inductances of the NCIs can be greatly reduced to achieve better current balancing performance. The added paralleling inductors are of small current ratings, which are only visible to DM currents. A prototype is implemented to validate the proposed method.

Three-phase four-leg four-wire (3P4L4W) three- level (3L) inverters have the ability to supply both balanced and unbalanced loads. This letter establishes common-mode (CM) and differential-mode (DM) circuit models for the 3P4L4W 3L inverter. The 3L phase-leg CM voltage is determined by the voltage balancing control (VBC) for the split dc-bus voltages, that the DM load voltages are subject to the DM voltage control for the 3L phase-leg, and that the CM load-voltage is subject to the control for the fourth phase-leg. On this basis, a decoupled modulation is proposed where the 3L phase-legs are modulated to attain VBC and closed-loop DM load-voltage control, whereas the fourth phase-leg is independently modulated to realize the closed-loop CM load-voltage control. The proposed work has been experimentally verified, showing that the 3P4L4W 3L inverter with this decoupled modulation scheme can provide well-balanced ac load voltages and low total harmonic distortion (THD) for any type of ac loads: balanced, unbalanced, linear, and nonlinear.

This paper proposes an intensive study for common-mode voltage (CMV) elimination/reduction in a five-level dual T-type multilevel converter (5LDT-MLC) drive. An advanced and fast model predictive control (MPC) approach is developed for CMV reduction (CMVR) and CMV elimination (CMVE) based on preselection of the switching states (SS). In addition, the proposed approach considers the torque control and the capacitor balancing of the proposed drive as essential aspects of MLC drives. A detailed study for the impact of the converter SS on the CMV is presented. The main features of the proposed MPC approach are reducing the complexity of the cost-function, the tuning burden of the weighting factors, and the computation time by more than 80% compared to conventional MPC techniques. A hardware implementation based on Silicon Carbide (SiC) T-type MLC is built. The experimental results demonstrate the effectiveness of the proposed MPC approach to mitigate/eliminate the CMV along with achieving the torque command and balancing the DC link capacitors. Unlike conventional CMVR techniques, the proposed approach reduces the CMV by 75% of its normal values without jeopardizing the harmonic contents, drive efficiency, and flux as well as torque ripples.

An integrated zero common mode voltage (ZCMV) modulation algorithm is developed in this research for dual-parallel neutral-point-clamped (NPC) inverters treated as an integrated system. While the conventional methods achieve CMV elimination with the cost of worse harmonic performance, the proposed method guarantees zero CMV and better current quality simultaneously by taking advantage of the extra space vectors provided by paralleling. Specially designed switching sequences are developed to maintain a balanced neutral point of DC-bus and ensure the averaged circulating current being zero, which is critical to the parallel operation and normal function of NPC inverters. In addition, although the switching sequence design is complicated, a simple approach is proposed and implemented on a commonly used digital signal processor (DSP). A laboratory prototype is also developed and used to test the system performance under steady-state conditions and dynamic process in grid-connected operation. Compared with conventional ZCMV modulation, experimental results verify the effectiveness of the integrated modulation in eliminating CMV, in addition to the dramatically reduced output current distortion.

based on the characteristics that the magnitude of active-current vector in the rectifier stage is zero when the zero-voltage vector is used in the inverter stage, a novel Discontinuous Pulse Width Modulation (DPWM) strategy for the indirect matrix converter is proposed in this paper to reduce the common-mode voltage (CMV). In this DPWM strategy, the reference current vector in the rectifier stage is synthesized by two adjacent active-current vectors, and the reference voltage vector in the inverter stage is synthesized by two adjacent active-voltage vectors and one zero-voltage vector. When the inverter stage utilizes one zero-voltage vector, the active-current vector with zero magnitude among the two adjacent active-current vectors, which produce smaller CMV, is selected to apply in the rectifier stage. The DPWM strategy reduces the peak magnitude of common-mode voltage by 42.3% while maintaining the advantages of the traditional DPWM modulation strategy such as less hard switching times in a carrier period, wide voltage transfer ratio, and input/output performance. Finally, the effectiveness of the modulation strategy is verified by simulation and experiments.

In transformerless photovoltaic (PV) generation system, the neutral-point (NP) voltage balancing and the ground current reduction of three-level inverter are carefully regulated using space vector modulation (SVM) scheme. Nevertheless, in low-voltage ride-through (LVRT) operation, the simultaneous reduction of NP voltage oscillation and common mode voltage (CMV) has not been researched yet. To overcome these issues, a selective SVM (SSVM) strategy is proposed in this paper. First, the NP voltage oscillation of three-level inverter in LVRT operation is analyzed in detail, which reveals that the NP voltage is affected by phase currents and duty cycles. Based on the location of output voltage and the direction of grid currents, the correct small vectors are selected under different power factor angles. Then, the small vector force (SVF) including the grid currents and duty cycle on NP voltage is proposed for the first time. According to the value of SVF, the optimal small vector having the most effective impact on NP voltage among the correct vectors and switching sequence are determined. With the proposed method, the NP voltage oscillation and CMV are reduced simultaneously in LVRT operation. Finally, the effectiveness of the proposed method is verified with experimental results.

This paper presents a control method to balance, in average, the DC-link capacitor voltages while injecting power to the grid using an h-bridge neutral-point clamped five-level inverter grid-tied through an LCL filter. The method exploits the structure of a particular model representation of the system comprising a differential-mode part and a common-mode part, which turn out to be decoupled from one another. These decoupled representation enormously facilitates the control design as it can be performed as two independent processes as well. The first design process involves the differential-mode model part and focuses on the grid current injection, while the second design process focuses on the balance of the DC-link capacitors voltages, and is based on the common-mode model part. Out of this, two control components are derived, namely differential-mode and common-mode control components, which are later recombined to form the two control signals, one per inverter branch, required as references in a conventional modulation algorithm to generate the switching sequence. Numerical and experimental results are performed to evaluate the performance of the proposed controller for the h-bridge neutral-point clamped inverter subject to those interconnections.

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

An equivalent Simulation Program with Integrated Circuit Emphasis (SPICE)-based circuit is derived from the proposed small signal averaged model of double-input Cuk-Buck DC-DC converter so that the power flow coupling effect amongst input/output ports is easy to be analyzed in terms of circuit theory rather than pure mathematics. Based on the equivalent SPICE-based circuit, common mode and differential mode power flow decomposition is presented to unveil the power flow coupling between three ports, and furthermore benefits frequency response analysis. It is shown that common mode perturbation analysis reveals the power flow coupling amongst input and output ports, whereas differential mode perturbation analysis does the power flow coupling between input ports. Meanwhile, the explanation of circuit knowledge is provided for power flow coupling effect. Particularly, it is found that the ocurrence of the pseudo resonant phenomenon is the result of counteract effect of the common mode and differential mode components in power mismatched condition. Besides, the application of frequency-selective decoupling is proposed to weaken the power flow coupling between ports. Finally, theoretical analysis is verified by experimental ones. These results are useful to understand coupling effects in multiple-input converters (MICs) and provide a guidance to the controller optimization and engineering application.

This paper presents a novel method to design multiple-input multiple-output (MIMO) antennas based on characteristic mode analysis (CMA), which is different from utilizing individual excitation of each characteristic mode for high isolation. The CMA is performed to design a pair of symmetric slots on two connected dipole antennas (a MIMO dipole pair), so that two desired characteristic modes can be generated at the same frequency, one of which is in common mode and the other in differential mode. Hence, when one antenna element is excited, the two characteristic modes combine and cancel each other at the other antenna element, leading to high port isolation. The designed dipole pair is applied for use in 2G/3G/4G MIMO base-station arrays. Simulation and measurement results show that the antenna achieves a wide impedance bandwidth of 1.7-2.7 GHz (45.5%), low coupling below -20 dB, low cross-polarization below -20 dB, high efficiencies over 85%, and stable radiation patterns within the entire band. The results verified the advances of the proposed decoupling method, i.e., simplicity, effectiveness, wide bandwidth, good radiation, etc.

In this article, a common-mode noise filter with a wideband suppressing and dual-band high absorbing common mode filter, which is called absorptive common-mode filter, is proposed. The filter is constructed by a reflective-type common-mode filter, a phase matching, and an absorber. It is composed of three layers with 14.98 mm × 9.585 mm. The broadband common-mode noise suppression can be achieved by positioning multiple transmission zeros. By using dual-band phase matching and an absorber, the dual-band absorption can be realized. The frequencies are in the range of 2.4 to 2.5 GHz and 5.17 to 5.33 GHz, respectively. The positioning of transmission zeros and absorption points at those frequencies leads to a high absorption efficiency. The simulation result shows that the common-mode suppression, which is below −10 dB, is from 2 to 11 GHz. The fractional bandwidth is 138%. The differential-mode signal keeps integrity in the range from DC to 12 GHz. The absorption efficiencies in the two frequency sections are 97% and 96%, respectively. The experiment results show only slight differences from the simulation results.

A non-isolated fast charger is proposed for electric vehicle (EV) battery system. The leakage current can be reduced by the novel charging system without bulky transformer. A zero sequence voltage control method is developed to stabilize the common mode voltage thus reduce the leakage current. The proposed fast charger includes two energy conversion stages: DC/DC converter for battery side control; DC/AC converter for grid interface and common mode voltage control. The parameters of the system with LCL filter are analyzed and optimized for a better performance of grid interface. Grid service functions are designed for the fast charger to provide grid voltage/frequency compensations. High power (22kW) and high efficiency 99% are achieved with low leakage current 20mA. The experiments are implemented to verify the proposed fast charger system.

In this paper, balance technique is applied into two-channel interleaved three-phase acdc converters with critical conduction mode based soft switching modulation. By adding additional inductors and coupling them with the original ones, the realization of the balance becomes possible with proper design; thus reducing the common-mode (CM) EMI noise. The balance condition is derived, and the impact of balance technique on the circuit operation especially on the switching frequency variation is quantified in order to provide the design guideline. Based on the application of balance technique, instead of the commonly used litz-wire based inductors, PCB winding coupled inductors are adopted and designed to effectively achieve the reduction of CM EMI noise. The design methodology and process are presented, and the design trade-off is made between the inductor loss and the inductor footprint. Finally, the effect of CM EMI noise reduction and the system efficiency with balance techniques and PCB winding magnetics are tested on a 25-kW SiC-based soft-switching three-phase acdc converter prototype.

In this paper, an active electromagnetic interference (EMI) filter is designed to reduce the DC side common mode (CM) EMI in motor drive system. Different from the traditional passive EMI filter which is added in the main circuit, the designed AEF in this paper is added in the grounding circuit which is connected between motor frame and the ground and it can be decoupled from the main circuit. By properly setting the components value, the DC side CM EMI can be suppressed while maintaining a low motor frame voltage. The structure of the AEF is simple and the volume of the AEF can be kept small. The operation principle of the AEF is introduced first and the performance of this AEF is evaluated through simulation. Experiment results verified the effect of this AEF that it can suppress the DC side CM EMI and the motor frame voltage can be kept low.

As the increase of power and voltage level of back-to-back three-level NPC converters, the high-amplitude and high-frequency common-mode voltage (CMV) has become an urgent problem. To address this, a CMV elimination method based on PWM pulse alignment for back-to-back three-level NPC converter is proposed. On this basis, a neutral-point potential balance method based on zero-sequence voltage (ZSV) is also proposed. In order to decouple the CMV elimination and the neutral-point potential balance, a same optimal ZSV is injected into both the rectifier and inverter sides and the CMV elimination will not be affected. Simulation and experiments are presented to verify the effectiveness of the proposed method.

A differentially fed duplex filtering dielectric resonator antenna (DFDRA) is proposed. This DFDRA combines the functions of the duplexer, the filter and the antenna into one highly integrated multifunctional module. A dual-mode substrate integrated waveguide (SIW) cavity working as the common feeding structure operates at two orthogonal modes at the lower and higher channel and is differentially fed by two pairs of differential input ports. The DRA working as the common radiation element operates at two orthogonal modes at two channels respectively and is excited by two cross slots etched on the top of the SIW cavity. High-isolation between the two channels is realized due to the two pairs of orthogonal operating modes of the DRA and SIW cavity. Measured results show that the balanced DFDRA can operate with differential mode 10dB impedance bandwidth of 2.7% (5.07-5.21 GHz) and 2.6% (5.72-5.87 GHz), the peak realized gains of 4.6-4.9 dBi and 4.8-5.1 dBi for two channels respectively. The isolation between the lower and higher channels is greater than 75dB. Good common mode suppression is realized.

The modified LCL (MLCL) is commonly applied in PV string inverters to suppress the leakage current and enhance the EMI performance of the grid current. However, the potential risk of resonance appears in the common mode (CM) loop caused by the MLCL filter. In this paper, the CM model of the inverter is firstly built considering the inductance saturation. It is found that the variable inductor brings phase margin decreasing problem and additional resonance points in the CM loop. To suppress the CM resonance (CMR), novel passive and active damping strategies are explored in this paper. The improved passive damping (IPD) strategy is realized by introducing a paralleled RC unit which greatly reduces the damping resistor losses without affecting the damping performance. Besides, a novel active damping strategy (NAD) is proposed to compensate the time delay and to raise the phase margin. Moreover, considering the gradient mutation issue brought by the discontinuous pulse width modulation (DPWM) scheme, an anti-saturation PWM (ASPWM) scheme is applied to eliminate the oscillation. Finally, experiments are conducted on an 80 kW PV string inverter. After applying the proposed CMR damping strategy with the ASPWM scheme, CMR is fully eliminated in the whole power range despite the grid condition.

In this article, a novel circuit is proposed to synthesize absorption common-mode filters (A-CMFs) in only one stage, which can be implemented with different kinds of transmission lines. This proposed one-stage absorption circuit has been derived with analytical equations, and design formulas are found to determine circuit parameters. To validate the proposed circuit and derived formulas, an intuitional structure composed of a meander slotline (MSL), a straight differential pair, and one resistor is proposed. Moreover, a technique named meander asymmetrical coplanar strip (MACPS) has also been developed to reduce the size of MSL-type A-CMF by up to 26%. Finally, the proposed test sample of MACPS-type A-CMF is fabricated in a two-layer printed circuit board (PCB) and measured. The common-mode (CM) noise absorption efficiency of above 80% can be obtained from 2.33 to 2.67 GHz to eliminate CM noises in the Wi-Fi 2.4 GHz band. Besides, the MACPS-type A-CMF provides an excellent differential-mode (DM) signal integrity. The −3 dB bandwidth of DM insertion loss can reach 7.5 GHz, and the measured eye diagram of the proposed work is identical to that of the reference board even the transmitted data rate is up to 16 Gb/s. To our best knowledge, the smallest A-CMF implemented in a two-layer PCB is achieved in this article with the electrical dimension being only 0.0358 λg2.

Multiphase space vector pulsewidth modulation (SVPWM) method has gained much attention with the growing interest in multiphase motor drives. Conventional multiphase SVPWM becomes more complex with the increase of phases, while simplified multiphase SVPWM is required for industrial applications. In addition, common-mode voltage (CMV) is the main cause of motor bearing damage and winding insulation breakdown for electrical drives. In this article, a simplified and generalized SVPWM method with CMV reduction is proposed for multiphase drives. The proposed SVPWM is intuitive and universal for arbitrary two-level multiphase inverters with odd phases, and CMV is restricted within ± V dc/2 N ( N is phase number). Experimental results verify theoretical analysis and effectiveness of the proposed method.

In this paper, a single-layer planar single-ended-tobalanced crossover has been proposed, which has a wideband filtering differential-mode response, wide path-isolation bandwidth, and an excellent common-mode suppression. The complete design procedure and rigorous derivations are demonstrated based on the even-/odd-mode analysis. A 3.5 GHz prototype has been designed, simulated and measured. Finally, the measured 15-dB differential-mode filtering bandwidth and 10-dB common-mode transmission bandwidth are 37.38% and 77.33%, respectively. Besides, a 117% bandwidth of 10-dB path-isolation is also achieved. Moreover, the bandwidth of 22-dB common-mode-to-differential-mode conversion is 143% over the frequency range of 1-6 GHz. This proposed crossover can be an excellent candidate for constructing balanced and unbalanced wireless communication systems.

This article proposes new common ground bridgeless power factor correction rectifiers suitable for use in any application which requires a positive or negative dc power supply. The main advantage of the proposed rectifiers, compared to previous works, is the provision of the common ground between input and output, which eliminates electromagnetic interference (EMI) associated with high rates of change of voltage and consequently reduces the need for EMI common mode filtering. The converter also provides step-down and step-up operation, and facilitates positive or negative output voltages with a low number of semiconductor devices operating simultaneously. High power factor, acceptable grid-side current quality, and high efficiency are also achieved. Two variants are presented, referred to as type-I and type-II, which offer common ground positive and negative dc voltages, respectively. Closed-loop control of the converters is provided by a dead-beat current controller in the inner loop. Experimental results are presented for a 500-W prototype, operating from 220 and 110 Vrms input to $\pm$ 48 and $\pm$ 200 Vdc output. The experimental results demonstrate the capability for step-down and step-up ac-to-dc power conversion with a peak efficiency of 96.8% and 96.6% in the positive and the negative outputs, respectively.

Impedance-source based solar PV systems are capable of achieving both voltage boosting and inversion in a single stage, resulting in a simple design thereby enhancing reliability. One of the major concerns of PV systems is their leakage current, as it can cause hazardous operational insecurity and reliability. This paper introduces a quasi Z-source based five-level inverter, which displays the following advantages: (i) reactive power handling capability, (ii) single-stage boosting, (iii) shoot-through immunity, and (iv) reduced leakage current based on VDE 0126-1-1. The proposed single-stage power converter is constituted by the fusion of a boosting stage, consisting of two back-to-back connected quasi-Z-sources, with a 5-level inverter produced by the combination of T-type and neutral point clamped (NPC) arms. The problem of the leakage current is addressed by a modified modulation technique and a passive filter structure, which filters high frequency variations in the common mode voltage (CMV). The working principle of the proposed power converter and the effectiveness of the modulation scheme to reduce the leakage current are assessed with the aid of simulation studies in both stand-alone and the grid-connected modes. The simulation results are experimentally validated with the aid of a laboratory prototype of 500 W rating.

The insulation monitoring technique for converter transformers has been explored using characteristic harmonics in the voltage source converter (VSC) system by the authors. The previous work enables the monitoring of aged groundwall insulation but cannot cover other insulation components. In order to explore the possibility of multitype insulation aging monitoring, in this article, we first derive an advanced model considering unevenly distributed circuit parameters along transformer windings and their frequency-dependent feature. Model improvements provide an accurate tool to describe multitype insulation in a wide frequency range. Based on the advanced model, a novel wideband common-mode (CM) impedance-response-based monitoring strategy for the VSC-connected transformer is proposed to achieve the evaluation of the aging in different insulation components. An illustrative case is studied on a 15 kVA transformer driven by an industrial inverter. Offline and online experiments are conducted to prove the effectiveness of the advanced model and the proposed strategy. Compared with the existing methods, the CM impedance-response-based strategy enables the online monitoring of multitype insulation components in an effective and noninvasive manner. In addition, the aging severities can be estimated reliably, even at incipient stages.

High common-mode rejection ratio (CMRR) of an analog front end (AFE) requires high intrinsic CMRR of the front-end amplifier with high input common-mode (CM) impedance. This article presents a common-mode replication (CM-REP) technique, which replicates the input CM voltage over the front-end amplifier. By eliminating the CM current flow and its mismatch effect, CM-REP improves CMRR and input CM impedance simultaneously. Implementation considerations regarding the input CM range, on-chip, and off-chip parasitics have been discussed with practical techniques incorporated with the proposed CM-REP. Fabricated in a 0.18-μm CMOS technology, the measured instrumentation amplifier (IA) exhibits >130-dB CMRR and 50-GΩ input CM impedance at 50/60 Hz concurrently. The >110-dB CMRR is achieved with input CM up to 900 mVpp and >102-dB total CMRR (TCMRR) is obtained with 1-MΩ || 10-nF mismatch of source impedance. The prototype consumes 1.86 μA from a 1.8-V supply and occupies an active area of 0.227 mm².

In multiphase induction motor drives, lowering the common-mode voltage (CMV) reduces motor insulation degradation and the existence of destructive bearing current. For this investigation, a five-phase two-level voltage source inverter (FPTL-VSI) fed five-phase induction motor (FPIM) drive is used. FPTL-VSI produces increased CMV, which cannot be totally removed. Moreover, CMV can be reduced by 80% in contrast to its peak-to-peak value with suitable selection of small and large voltage vectors in a space vector pulsewidth modulation (SVPWM) scheme. Direct torque control (DTC) combined with the SVPWM scheme can accomplish such reduced CMV performance at constant switching frequency. To provide better speed and torque control, two virtual vector (VV) based SVPWM-DTC (DTC1 and DTC2) methods are proposed in this study. Over a wide range of modulation index, the influence of each voltage VV on motor drive speed and torque response is investigated. The proposed DTC1 and DTC2 schemes are validated under steady-state and dynamic conditions over a wide range of speed fluctuations using a high-power laboratory prototype of $3.8\,\text{{k}W}$ FPIM drive. The efficacy of the proposed DTC1 and DTC2 is compared to the current literature by evaluating the effectiveness of CMV and the switching frequency.

In ac–dc power conversion system, modular multilevel converter (MMC) has been a promising technology, especially for high-voltage application. In such kind of application, the common-mode voltage (CMV) generated by power electronic switching can cause damage to electrical components and increase the electromagnetic interference (EMI) to the system. Hence, this article proposes a modulation scheme to reduce the CMV of MMC applied in high-voltage system, such as high-voltage dc. Usually, MMC consisting of numerous submodules (SMs) adopts the nearest level modulation (NLM) with the low switching frequency, so the CMV of the NLM scheme is analyzed, which indicates that the peak value of CMV is one-third of SM voltage. If one more or one less SM is turned on compared with NLM, the CMV caused by modulation can be eliminated theoretically. Subsequently, a modulation scheme based on the nearest zero CMV vector (NZCMVV) to reduce CMV is proposed for MMC. The NZCMVV scheme utilizes the two adjacent levels as candidate levels, and the theoretical ZCMVVs are picked out. Finally, the ZCMVV closest to the reference vector is selected to approximately replace the reference. The proposed method is simple and easy to implement. Simulated and experimental results validate that the proposed scheme can reduce CMV and CM current compared with the traditional NLM method.

Designing an efficient, compact, and optimized electromagnetic interference (EMI) filter for the next generation high-frequency switched mode power converter while maintaining a small form factor with high power density, requires adequate research and development effort. This article presents a systematic as well as unified approach to design the EMI filter for any power electronic converter, particularly for three-phase ac–dc active boost rectifier systems. Since the differential mode (DM) filter stage consumes a major part of the EMI filter volume and weight, DM filter design optimization is a necessary yet challenging task to attain a higher power density. This article theoretically demonstrates the design steps for choosing the appropriate filter component values and number of filter stages to achieve the smallest volume of the DM EMI filter. Furthermore, to design an optimized common mode (CM) filter stage, a research effort has been made for estimation of the CM noise corner frequencies followed by multiconstraint volume optimization through a detailed mathematical noise modeling of the converter. While the validation of the proposed design methodology is done through MATLAB simulation, an experimental verification is also performed by designing the optimized EMI filter for a 2.3-kW proof of concept of a three-phase boost power factor correction converter to comply with the stringent EMI requirements of DO-160F standard.

An efficient multiconductor transmission line (MTL) model of a shielded twisted wire pair (TWP) with apertures on its sheath is developed for predicting common mode (CM) and differential mode (DM) currents induced in the shielded TWP cable. Its transfer impedance and admittance with one-line apertures on its sheath are derived in a closed form. Therefore, the MTL equations are formulated and solved to obtain the CM and DM currents induced in the shielded TWP. Moreover, the proposed MTL model is generalized to be applicable for the braided–shielded TWP, in which the transfer impedance and admittance are formulated analytically. Results showed that the induced DM current inside the braided–shielded TWP is suppressed dramatically due to the uniform structure of the cable. The models are validated by comparing their results with those obtained by the commercial software FEKO; good agreements are obtained.

For ac/dc power conversion applications like server power supply, telecom power supply, and on-board charger of an electric vehicle, the rising electricity demand has presented challenges toward high efficiency and high power density. The cascaded H-bridge (CHB) based multilevel power factor correction (PFC) converter has much higher power density than that of traditional boost PFC converter. However, the CHB-PFC converter has multiple floating dc outputs, which leads to a common mode (CM) electromagnetic interference (EMI) issue due to the parasitic capacitance of cascaded dc/dc stages and layouts and distributed noise sources existing in the ac/dc system. Thus, a large EMI filter is necessary for the PFC system that sharply degrades the system's power density. In order to quantify the CM noise caused by the floating outputs and cascaded parasitic capacitance, a unified equivalent CM circuit model is derived in this article, which decouples the effects among the multiple CM noise sources in the CHB converter. Based on the derived circuit model, a mirror-bridge phase-shift modulation is proposed to cancel the CM noise within the CHB converter itself. A single-phase 2-kW CHB PFC prototype has been built up to verify the analysis, and 40-dB CM noise reduction compared with conventional unipolar modulation is achieved by the proposed modulation scheme.

Virtual space vector pulsewidth modulation (VSVPWM) provides a new approach to neutral point voltage (NPV) control and common mode voltage (CMV) suppression. Few values of coefficients configured in the virtual vectors cannot adjust the NPV continuously. An improved VSVPWM (IVSVPWM) with active neutral point voltage control (ANPVC) and CMV suppression is proposed in this article. Continuously variable coefficients configured in the virtual vectors adjust the NPV actively and continuously for any load power factor over the full modulation indexes. Failure of CMV suppression is analyzed, and the undesired vectors with high CMV are avoided by limiting the range of the variable coefficients. The limited variable coefficients and the selected basic vectors with low CMV suppress the CMV effectively. Simulation and experimental results are given to validate the proposed novel IVSVPWM, which can achieve quicker ANPVC and reduce CMV to half of the conventional VSVPWM simultaneously.

This paper presents Space Vector Modulation (SVM) sequences that reduce Common-mode Voltage (CMV) in Dual Three-phase Asymmetrical Induction Motor (DTAIM). First, existing SVM techniques namely Standard SVM (SSVM) and CMV1 are studied and then, three new switching sequences CMV2, CMV3 and DCMV3 are proposed which reduce peak magnitude of CMV by 66.8% in comparison with SSVM technique. In SVM techniques, to obtain least CMV, zero vectors are usually replaced by two opposite large Active voltage Vectors (AVs) with equal time duration. In such topologies like CMV1, total six AVs are utilized to synthesize reference vector. The proposed CMV2 utilizes only five large AVs to synthesize reference vector and reduces CMV. Selection of five neighbouring AVs in proposed techniques yields reduction of harmonic flux trajectories and stator current ripple. Additionally, two more switching sequences (CMV3 and DCMV3) are developed that is related to utilization of specific zero voltage vectors in all sectors (7 and 56) and produce zero CMV. The CMV and stator current ripple are considered as performance parameters for different SVM techniques. All SVM techniques are analysed by analytical results, computer simulations, and using prototype test setup of DTAIM fed by Dual Three-phase Voltage Source Inverters (DTVSIs).

An improved two-stage model predictive current control (MPCC) for three-phase three-level converters in the paper, which can simultaneously achieve common-mode voltage (CMV) reduction, effective dc-link capacitor voltage control, and decreased computational burden, is proposed. Compared to the other current control strategies, it has the capability of handling multiple control objectives and possesses a simple structure. Furthermore, it greatly reduces the CMV since the peak CMVs of all the candidate voltage vectors are constrained to be less than one sixth of the dc-link voltage. In addition, an optimal two-stage voltage vector selection mechanism is employed in the proposed method. It helps to significantly reduce the computational complexity. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

The modulation strategies of dual active bridge (DAB) including single phase-shift (SPS), dual phase-shift (DPS), and triple phase-shift (TPS) have been proposed to optimize the efficiency, eliminate the reactive power, and release the current stress. While the previous literature focuses on the accurate loss model in steady states or small-signal analysis for dynamic response, the common-mode (CM) model has been largely ignored. The main contribution of this article then is to propose an analytical CM model for DAB, which considers the CM parasitic capacitors including those of grounded heatsink and transformer windings. Based on such model, the CM performance is compared among different modulation strategies. The impact of two H-bridge on the input and output CM voltage has been addressed. A prototype based on SiC devices is used to verify the proposed analytical mode under SPS, DPS, and TPS. It is found that while TPS improves the light-load efficiency it introduces the worst CM noise. Influence of the ZVS current setting on the CM performance is also discussed.

Transformer-less inverters (TIs) are widely used in photovoltaic (PV) applications owing to their low cost and high efficiency. However, the combined effect of high-frequency common mode voltage and PV parasitic capacitance burdens the TIs with undesired ground leakage current. In this article, a switched capacitor (SC)-based five-level TI is proposed. The negative dc rail of the proposed TI is directly connected to the grid neutral, thereby completely eliminating the leakage current. Besides, it has the inherent capability of boosting the output voltage without using any magnetic component or additional circuitry. For several instances in every fundamental cycle, the SCs are paralleled with the input voltage source and hence are self-balanced. The proposed topology does not have any limitation on modulation index since the SC voltages are self-balanced and hence less complex or no dedicated control scheme is required. Further, a quantitative comparative study is presented, highlighting the benefits of the proposed TI regarding boosted voltage, elimination of leakage current, and reduced component count. Finally, in order to verify the performance of the proposed TI, detailed simulations followed by experiments on a laboratory prototype developed by using DS1202/1302 dSPACE controller are carried out and the results presented for both steady-state and dynamic conditions verify the feasibility of the proposed TI.

This article proposes a new pulsewidth modulation (PWM) strategy to reduce common-mode voltages (CMVs) in grid-connected two-level inverters. Reduction of CMVs is an important issue in the field of distributed energy resources (DERs) because CMVs at a high switching frequency cause ground leakage currents that lead to safety issues in the applications of DERs. In the proposed PWM strategy, each reference vector is split into two vectors during the PWM period. The peak-to-peak magnitude of CMV is reduced by one-third as the split vectors are synthesized without using zero vectors. The influence of the dead-time and its compensation in the proposed method are also described. Our proposed method can be easily implemented with carrier-based PWM. Simulation and experimental results are presented to verify the performance of the proposed strategy.

A three-phase three-level converter with an LCL filter has been used in the industry because of its low switching harmonics. However, it inevitably suffers from dc neutral-point imbalance, which may unnecessarily stress semiconductors and deteriorate power quality. The imbalance will, nevertheless, naturally rebalance, but it usually takes a long time. A common rectification is, thus, to add an active or a passive booster to speed up the balancing. An active booster requires sensitive sensors and control modification, which will increase the system cost and complexity. A passive booster is, therefore, preferred owing to its exemption of monitoring and control efforts. The existing three-phase passive booster, however, contains several extra separate LC components, which are normally not functioning during the balanced conditions. They should, hence, be reduced. One approach is to dual use the existing LCL (or other high-order) filter for both harmonic filtering and dc-link balancing. Topologically, it requires only the addition of one extra capacitor along the return common-mode path. Using newly formulated criterions related to sizing, harmonic, and modulation selections, the balancing performance of the resulting capacitive balancer has been evaluated comprehensively. Finally, an experimental prototype is built for testing the balancing mechanism under different operating conditions.

In order to effectively suppress the intractable high-frequency conducted common-mode (CM) electromagnetic interference (EMI) and reduce the dependence on the high-frequency performance of the EMI filter, this article proposes a separate floating heatsink based suppression method (SFHBSM). SFHBSM suppresses high-frequency CM EMI by improving both the CM EMI source and the propagation path. On the one hand, SFHBSM achieves the nonringing CM EMI source without introducing additional resistive loss, by properly designing the parameters of the SFHBSM, the ringing effect in the CM EMI source can be pushed into a narrow bandwidth in the very high-frequency domain, where the ringing effect can be naturally killed by the skin effect. On the other hand, the CM EMI propagation path of the SFHBSM-based power converter is mathematically deduced, verifying that the SFHBSM can provide effective blocking for the CM EMI propagation in the high-frequency domain. Experiments show that under the combined effect of the ringing suppression and propagation blocking, SFHBSM achieves EMI reduction in almost the whole high-frequency domain, and provides up to 35 dB attenuation in a two-level three-phase power converter. Besides, ablation experiments have been conducted to evaluate the individual and combined effectiveness of each part of the SFHBSM.

Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results.

This article presents a critical conduction mode (CRM) single-phase transformerless full-bridge inverter in a residential photovoltaic system. The CRM full-bridge inverter in bipolar mode features zero-voltage switching capability for the whole line cycle. This enables the inverter to push switching frequency up to hundreds of kHz and achieve high power density with high efficiency. However, CRM operation incurs nonconstant common mode (CM) voltage during the resonant period, causing high frequency leakage current. To minimize the leakage current, a new switching modulation strategy is proposed introducing triangular current mode (TCM) near the ac voltage zero crossing. The switching modulation scheme alleviates the CM voltage by shortening the resonant period and consequently reduces the leakage current. Then, discontinuous conduction mode is inserted between the CRM and TCM operation regions to improve light load efficiency. In this article, the basic operation principle of the CRM full-bridge inverter, impacts of CRM operation on the leakage current, and details of the proposed switching modulation method are discussed. Experimental results with a 2.4-kW prototype built with GaN devices validate its performance.

In this article, a compact co-polarized decoupled antenna for full-duplex application working at 1.71 GHz is proposed. The antenna is composed of two back-to-back air-dielectric planar inverted-F antennas (PIFAs) with zero edge-to-edge distance. The whole system is included in a compact volume of $0.45\lambda _{\mathrm {\mathbf {0}}} \times 0.45\lambda _{\mathbf {0}} \times 0.02\lambda _{\mathbf {0}}$ . The proposed antenna is designed based on the common mode (CM)/differential mode (DM) cancellation theory and its design guideline is illustrated in detail. Isolation maximum of 42 dB, broadside gain of 6.7 dB, and efficiency of 90% have been achieved in the proposed structure. There is a 1.9 dB gain difference between the broadside gain and the maximum gain. The proposed antenna shows its potentials in the radio frequency front-end incorporate design.

Many reduced common mode voltage (CMV) modulation methods have been proposed for three-level inverters. However, most of them suffer from large current distortion because only part of the available base vectors is utilized. The interleaved paralleling can reduce both CMV and the output current distortion, though the CMV reduction is limited and large zero-sequence circulating current (ZSCC) is inevitably caused by the phase-shifted carriers. To further reduce the CMV while maintaining smaller current distortion and ZSCC, a five-level reduced CMV (RCMV) modulation method is proposed in this article, which treats the parallel inverters as a whole. Theoretical analysis reveals that the integrated modulation provides additional base vectors that contribute to smaller total harmonic distortion (THD) of the current, and the selected vectors ensure the nearest-three-vector synthesis and half-reduced CMV. The switching sequences design and neutral point balancing strategy are also developed for dual-parallel three-level inverters, ensuring that the average circulating current is zero and the neutral point voltage is balanced, which are both critical to the proper operation of parallel inverters. Superior performance in terms of CMV, THD, and ZSCC provided by the proposed method in comparison with conventional modulation is verified by comprehensive simulation and experimental results.

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.