32 results on '"Entrena, Luis"'
Search Results
2. Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs
3. Analysing the influence of memory and workload on the reliability of GPUs under neutron radiation
4. Using Approximate Circuits Against Hardware Trojans
5. Supervised Triple Macrosynchronized Lockstep (STMLS) architecture for multicore processors
6. Formal Verification of Fault-Tolerant Hardware Designs
7. Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA designs
8. Analyzing Scaled Reduced Precision Redundancy for Error Mitigation Under Proton Irradiation
9. Reliability Evaluation of LU Decomposition on GPU-Accelerated System-on-Chip Under Proton Irradiation
10. Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation
11. Comparison of Parallel Implementation Strategies in GPU-Accelerated System-on-Chip Under Proton Irradiation
12. Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS
13. Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique
14. A True Random Number Generator Based on Gait Data for the Internet of You
15. Towards a Dependable True Random Number Generator With Self-Repair Capabilities
16. Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches
17. A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications
18. Online Test of Control Flow Errors: A New Debug Interface-Based Approach
19. Using Benchmarks for Radiation Testing of Microprocessors and FPGAs
20. Efficient Mitigation of Data and Control Flow Errors in Microprocessors
21. Low-power design in aerospace circuits: A case study
22. Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects
23. A Co-Design Approach for SET Mitigation in Embedded Systems
24. Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection
25. Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits
26. Analysis of SET Effects in a PIC Microprocessor for Selective Hardening
27. Sensitivity Evaluation Method for Aerospace Digital Systems With Collaborative Hardening
28. Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures
29. Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening
30. SET Emulation Considering Electrical Masking Effects
31. Analysis of Turbo Decoder Robustness Against SEU Effects
32. Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.