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Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values.

A method that aims at analyzing the dynamic behavior of some two-phase switched-capacitor charge pump circuits is proposed. A recurrence relation on the voltages across the charging capacitors of a given two-phase charge pump circuit is developed. The output voltage and the accumulated charge of a charge pump circuit after any clock cycle were found by solving some basic matrix equations, with a specific loading current and some required initial conditions. The validation of the proposed method was done by SPICE simulations based on a 8 × linear, Fibonacci, and an exponential charge pump. The analysis results were also verified with the simulation results obtained from some charge pump circuits designed with the 0.18 μm CMOS process. Results show that the proposed method can yield a close estimation on the dynamic behavior of a charge pump circuit in most of the designs. We further found that the rising times for the exponential and Fibonacci charge pumps are shorter, especially when the conversion ratio is high, than that of the linear one.

This paper proposed an analytical model on the deterioration of magnetic sensitivity of sectorial split-drain magnetic field-effect transistors (SD-MAGFETs). The deterioration is governed by the trap fill rate at the channel boundary traps, which is geometric dependent. Experimental results are presented which show good consistency with the analytical derivation. The deterioration is the most severe at a sector angle of 54.6°, which shows a design tradeoff with sensing hysteresis. Design guidelines for sectorial SD-MAGFET to obtain high sensitivity hysteresis and slow sensitivity deterioration are also presented which provide important information for efficient design.

With X-ray photoelectron spectroscopy (XPS) measurements, we found in the N/sub 2/O-grown oxide that the nitrogen incorporation should involve the NO or N reaction with the Si-Si bond and P/sub b/ centers at the interface. Consequently, nitrogen content is very low and accumulated mainly at the interface. In addition, we found that the nitrogen atoms at the interface exist in the form of Si-N bonding and the interface oxynitride layer is a mixture of SiO/sub 2/ and Si/sub 3/N/sub 4/ clusters. This structure will result in several undesirable effects. It will give rise to the permittivity and bandgap fluctuations at the interface and hence induced gigantic surface potential fluctuation and mobility degradation in the channel of MOS devices. This bonding structure also explains the interface trap generation during the electrical stressing. The sources of trap generation are attributed to the Si-Si bonds, P/sub b/ centers, and nitride-related defects due to the over-constrained silicon atoms in the Si/sub 3/N/sub 4/ clusters at the interface.

This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3/Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.

This work presents an accurate approximation of the length of velocity saturation region (LVSR) based on the calculation of one-dimensional (1-D) electric field distribution near the drain region of MOSFET's. Results show that for short-channel devices (

Parasitic bipolar transistor (PET) induced breakdown characteristics in MOSFETs are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the breakdown voltage for the PET-induced breakdown can be increased by raising the temperature, increasing the channel length, and reducing the substrate resistance.

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44/spl sim/10 /spl mu/m.

A low-frequency (flicker) noise model based on the physics of trapping and detrapping of electrons at the silicon-oxide interface for MOS transistors in the linear regions is presented. Using the experimental results that the trapping and detrapping time constants are different for the same gate bias and temperature, both (V/sub G/-V/sub t/)/C/sub ox/ and C/sub ox//sup -2/ dependencies were obtained in the newly proposed model without introducing the mobility fluctuation term. Gate and temperature dependencies of the frequency index were also incorporated into the model. Results show that the proposed model yields a better correlation to the experiments than others, but there are still several experimental observations unexplained. Suggestions for further refinement of the model are also given. >

A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices with differently prepared gate oxides were used to study the process-induced trap distribution. Several peaks varying from sample to sample are found in a frequency index of noise spectrum versus temperature plot and are correlated with the discrete trap distribution across the bandgap of silicon. This method provides more information on traps as it circumvents the complexity of superimposing different traps which was encountered in the capacitance-voltage (C-V) method. Results, either compatible with others' work or consistent with data based on other measurements, show that the electronic trapping behavior in MOS structures is governed by two intrinsic traps located at 0.12 and 0.3 eV (both measured from the conduction band) for all kinds of oxides. In addition, dry oxidation was found to introduce an additional trap at an energy level of 0.23 eV, and annealing the gate oxide in ammonia at a high temperature (>1000 degrees C) results in an enhancement of the trap density of 0.43 eV below the conduction band edge of silicon, which was also observed in a quasi-static C-V measurement. >

A new approach to the current-voltage (I-V) characteristics formulation for short-channel MOSFET's by incorporating the channel length modulation, mobility degradation, drain induced barrier lowering, and threshold voltage variation into Pao-Sah's equation is presented. Results show that the calculated I-V characteristics agree well with the experimental ones for devices with effective channel length in the range of 0.44/spl sim/20 /spl mu/m. Compared with the existing models, the model has the advantages of less number of model parameters and simpler form of the current-voltage relationship. >