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In this work we study the limits of miniaturization of a 90-degree hybrid coupler working in the L, C and S bands, with respect to a number of performance parameters aimed at its application for balanced detection. We investigate the main effects responsible for the degradation of the performance of the devices during miniaturization, and establish the minimal dimension that such devices can have without significant degradation for photonic applications such as balanced detection. The miniaturized device in InP generic technology has a footprint of only 2200μ m2 , more than 5 times smaller than the conventional device used as reference. The scaling approach is based on the use of the number of propagating modes which are sustained in both the miniaturized MMI and port waveguides as scaling parameters. This approach allows us to generalize the miniaturization problem from a specific platform and offers a methodology which is flexible and transferable to multiple platforms. We tested the scaling methodology based on the number of modes in other platforms commonly used in integrated photonics, such as Si/SiO2(SOI), TriPleX or polymer platforms, obtaining comparable results and proving the universality of our approach, finally we performed a fabrication tolerance analysis of the miniaturized devices.

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Novel back-illuminated modified uni-traveling- carrier photodiodes (MUTC-PDs) are reported to demonstrate wide bandwidth and high output power performance at D-band (110–170 GHz) regime. A comprehensive design model is employed to predict and tune the frequency response by incorporating coplanar waveguides (CPWs) with different inductive peaking effects. As a demonstration, 4.5-μm-diameter photodiodes with two types of CPWs are fabricated to exhibit different frequency response profiles. Both PDs exhibit a 3-dB bandwidth over 150 GHz and the measured frequency responses are in excellent agreement with simulations. Thanks to the proper design of the CPW electrodes, the two PDs exhibit an output power roll-off of only 4.3 dB and 4.8 dB from dc to 170 GHz, respectively, and high saturation performance is maintained over the broadband frequency range of 130–170 GHz.

An indium phosphide photonic integrated circuit (PIC) was demonstrated for integrated path differential absorption lidar of atmospheric carbon dioxide (CO2). The PIC consists of two widely tunable sampled grating distributed Bragg reflector (SGDBR) lasers, directional couplers, a phase modulator, a photodiode, and semiconductor optical amplifiers (SOAs). One SGDBR laser, the leader, is locked to the center of an absorption line at 1572.335 nm using the on-chip phase modulator and a bench-top CO2 Herriott reference cell. The other SGDBR laser, the follower, is stepped in frequency over ±15 GHz around 1572.335 nm to scan the target CO2 absorption line. The follower laser is offset locked to the leader laser with an optical phase lock loop. An SOA after the follower laser generates a pulse at each frequency step to create a train of pulses that samples the target CO2 absorption line. The PIC components and subsystem are characterized and evaluated based on target performance requirements. The leader laser demonstrated a 236-fold improvement in frequency stability standard deviation when locked compared to free running and the follower laser frequency stability standard deviation compared to the leader laser was 37.6 KHz at a 2 GHz programmed offset.

A terahertz (THz) fundamental oscillator IC with high efficiency and compact chip size based on an indium phosphide (InP)-based resonant tunneling diode (RTD) is proposed. The oscillator is designed by utilizing a low-frequency bias stabilizer, along with utilizing a negative differential resistance oscillator topology. The oscillator is fabricated by using an InP monolithic THz integrated circuit multilayer process. The fabricated oscillator shows a high dc-to-RF power efficiency ( η ) of 0.274 % with a low dc power consumption of 3.4 mW and an RF output power of 9.3 μ W at an oscillation frequency of 692 GHz. The IC exhibits a chip size of 300 × 380 μ m2 excluding the measurement pads. The achieved η and chip size are good values among THz oscillators above 500 GHz reported to date.

The use of nanostructures over traditional bulk and thin-film solar cells (SCs) increases the efficiency per unit volume due to the coupled effects of intrinsic antireflection and strong excitation of resonance modes. The structural optimization of InP nanowires (NWs) provides a deep insight into the electrical and optical parameters of NWs influenced by structural morphology. Here, we propose a core–shell structure using n-InP NW as a core coated with PEDOT:PSS/MoO3 shell. We simulated the resultant structure using the finite difference time domain (FDTD) and device modules of Lumerical to investigate its optical and electrical behavior. The optical simulation predicts that a hole-selective layer over InP core increases the absorption of incident photons. An optimized thickness of shell reduces the required core material without affecting the ideal current density, resulting in low manufacturing cost. For core doping of $5\times10$ 18 cm−3, surface recombination velocity (SRV) of 104 cm/s, and minority carrier lifetime ( $\tau_{p}$ ) of 40 ns, an efficiency of ~25% can be achieved. In this article, we have also compared the optical and electrical characteristics of uncoated, PEDOT:PSS/InP NW and ITO/InP NW and electron-selective oxide-coated InP NW with our proposed structure and found that our proposed structure PEDOT:PSS/p-MoO3/ n-InP heterojunction NWSC exhibits better photovoltaic (PV) performance than the above-mentioned structures.

High-speed and robust optical beam-steering device will be the key component for various applications, such as LiDAR (light detection and ranging) and free-space optical communication. Optical phased arrays (OPAs) integrated on semiconductor chips have recently received increasing attention due to the high-speed operation, compactness, and low cost. In particular, indium phosphide (InP)-based OPAs are advantageous for high-output-power applications at 1.55- $\mu \text{m}$ eye-safe wavelength, owing to their capability of monolithically integrating active components, such as high-power lasers and optical amplifiers. In this letter, we design and fabricate, to the best of our knowledge, the largest-scale InP-based OPA and experimentally demonstrate its beam-steering operations. The fabricated OPA consists of 100 waveguides with carrier-injection-based phase shifters, densely integrated on 7 mm $\times5$ mm footprint. A focused beam width of 0.11° is steered across the free spectral range of 8.88°, corresponding to more than 80 resolvable points. This is the largest number of resolvable points obtained by a monolithic InP OPA. The response time of the OPA is confirmed to be less than 16 ns, which is limited by the driver circuit. This work paves the way for realizing compact beam-steering modules for high-speed and high-output-power imaging applications.

Avalanche photodiodes (APDs) are used in optical receivers of high-speed optical communication systems to improve signal-to-noise ratio over conventional photodiodes. Low excess noise characteristics are crucial for APDs to preserve the benefits associated with high internal gains. In this work, we presented room temperature data of avalanche gain and excess noise factors of Al0.85Ga0.15As0.56Sb0.44 APDs using pure and mixed carrier injection profiles. Using pure electron injection, the best possible excess noise performance for a given avalanche width was measured with an excess noise factor https://doi.org/10.15131/shef.data.15082455 )

In this letter, we present a 25-GSa/s wideband track-and-hold amplifier using 0.8- ${\mu }\text{m}$ indium phosphide (InP) process for high-speed analog sampling front-end. In this design, an active peaking input buffer is first used in the base–collector switching diode sampler. Moreover, it is carefully calculated and analyzed. The dominant pole in the signal path of the circuit is canceled by one zero produced by the active peaking structure; therefore, the bandwidth (BW) is extended. The experimental results show that a total harmonic distortion (THD) of less than −27 dBc and a spurious-free dynamic range (SFDR) of better than 32.5 dB are demonstrated at a 25-GSa/s sampling rate. In the hold mode, the isolation is better than −42 dB. In addition, it has an 0.156 ${f_{T}}$ BW from dc to 25 GHz within 160-GHz ${f_{T}}$ , which is a very competitive value compared with other reported track-and-hold amplifiers (THAs) using the InP process.

We fabricate a membrane InP-based electro-absorption modulator (EAM), in which an InGaAsP-based multiple-quantum-well (MQW) absorption region is buried with an InP layer, on Si-waveguide circuits. By optical coupling between the MQW absorption region and Si core, a low-loss and large-absorption-length (300-μm-long) supermode waveguide is designed to suppress electric-field screening at high optical input power. The EAM is fabricated by combining direct bonding of the MQW layer and regrowth of the InP layer on a thin InP template bonded on a silicon-on-insulator wafer. The fabricated membrane EAM shows an on-chip loss of less than 4 dB at wavelengths over 1590 nm and temperatures from 25 to 50 °C. Since the membrane lateral p-i-n diode structure is beneficial for reducing the RC time constant of a lumped-electrode InP-based EAM, the EO bandwidth of the EAM is around 50 GHz without a 50-ohm termination up to fiber-input power of 10 dBm. Using the device, we demonstrate clear eye openings for 56-Gbit/s NRZ and 112-Gbit/s PAM4 signals at temperatures from 25 to 50 °C.

In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/ $\mu \text{m}$ is achieved with an intrinsic gate capacitance of $0.39~\mu \text{F}$ /cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length ${L}_{g}=80$ nm has SS $_{\text {min}}=168$ mV/dec, dc transconductance ${g}_{\textit {m,e}} =1.0$ mS/ $\mu \text{m}$ at ${V}_{\text {DS}}=0.5$ V, and exhibits a peak cutoff frequency $\it f_{\!{T}} $ of 243 GHz, and a maximum oscillation frequency $\it f_{\text {max}}$ of 147 GHz at ${V}_{\text {GS}}=0.25$ V, ${V}_{\text {DS}}= {1}$ V.

We investigated theoretically a waveguided EAM (Electro-Absorption Modulator) based on ISBT (Intersubband Transitions) in an In(0.53)Ga(0.47)As/AlAs/AlAs(0.56) Sb(0.44) A-CDQWs (Asymmetric Coupled Double Quantum Wells) lattice-matched to InP at telecommunication wavelength ( $\lambda =1.55~\mu \text{m}$ ) which offers ultrahigh-speed and moderate voltage swing. Likewise, the temperature dependency in the In(0.53)Ga(0.47)As/AlAs/AlAs(0.56) Sb(0.44) A-CDQWs was investigated at different temperatures from 300 K to 400 K and evidently the InP-based ISB (Intersubband) modulator offers better temperature stability (~ 0.05 nm/C) compared to the InP-based IB (Interband) modulator. The EAM investigated here is anticipated to have a RC-limited speed ( $f_{3d\,B}$ ) of ~300 GHz with insertion loss of 5.1 dB, 10 dB extinction ratio and 5.18 dB/V modulation efficiency at a peak-to-peak voltage of 2.0 V which can support a data rate of up to 600 Gbps and beyond.

A photoreceiver consisting of indium phosphide (InP) balanced photodiodes (PD) on Si $_3$ N $_4$ waveguides and a transimpedance amplifier (TIA) fabricated in a silicon germanium (SiGe) BiCMOS process is demonstrated. The InP PDs, heterogeneously integrated on a silicon substrate, achieve external (internal) responsivities of 0.75 (0.9) A/W, bandwidths of 4 GHz, and common mode rejection ratios (CMRR) of greater than 40 dB when illuminated differentially. The TIA achieves 74 dB $\bf \Omega$ of transimpedance gain with a 1 dB peak, a bandwidth of 3 GHz, and a low equivalent input noise current density of 7.2 pA/ $\sqrt{Hz}$ when loaded with a C $_{PD}$ of 380 fF. The full photoreceiver achieves high conversion gain of more than 2 kV/W up through 2 GHz, and a low NEP of 8 pW/ $\sqrt{Hz}$ up through 1.6 GHz. The photoreceiver optical CMRR is measured to be 36 dB.

This letter describes the design and measured performance of an $E$ -/ $W$ -band GaN MMIC low-noise amplifier based on a 90-nm T-gate GaN technology. The GaN technology is characterized by a peak fT of 145 GHz and an NFmin of ~1.2 dB at 50 GHz. The LNA is comprised of a four-stage common-source amplifier designed to operate over a 70–110-GHz frequency band. From 70 to 89 GHz, the amplifier achieves 15–17.9 dB of gain and an NF of 3.5–4.2 dB over a 75–83 GHz measured subband. From 90 to 110 GHz, the amplifier achieves a gain from 15.8 to 19.2 dB and an NF of 3.3–3.8 dB over a 91–96-GHz measured subband. These are believed to be the lowest NFs achieved from a single GaN amplifier covering both $E$ - and $W$ -frequency bands. The MMIC is $2.4\times1.3$ mm2 in size and consumes 200 mW of dc power from a 5-V supply. The GaN LNA can be integrated with a PA and RF switch to form a compact GaN TR MMIC solution.

This work presents a high efficiency, compact 80–110-GHz InP power amplifier (PA) based on stacked common base (CB) topology and a counterpart design using conventional stacked common emitter (CE) topology. The comparison between the two exhibits that the former delivers higher power gain, superior-gain compression behavior (linearity), and higher back-off efficiency in $W$ -band in 250-nm InP heterojunction bipolar transistor (HBT). At 90 GHz, the stacked CB/CE PA achieves 11.8 dB/6dB gain, 33%/34% peak PAE, 16.8%/14.5% PAE at 6-dB back-off, and Psat of 18.7 dBm/19.6 dBm. Modulation test exhibits an EVM of 2.38% at 11.8-dBm average power supporting 3 Gbps 64-QAM for the stacked CB PA. The stacked CB PA with 17.9–18.9-dBm Psat across 80–110 GHz demonstrates one of the highest efficiency, broadband and linear PAs in $W$ -band using InP technology.

The effect of atomic-layer-deposition (ALD)-derived Al2O3 passivation layer on the interface quality of Er2O3/Al2O3/InP laminated stacks and the improvement of electrical performance has been investigated systematically. The chemical bonding states measured by high-resolution X-ray photoelectron spectroscopy (XPS) reveal that the ALD-derived Al2O3 passivation layer can effectively inhibit the diffusion of substrate elements to optimize the interface quality. Electrical characterizations show that the optimized sample has demonstrated improved electrical properties, including the large dielectric constant of 20 and the suppressed leakage current density of $4.10\times 10^{-7}$ cm2. In addition, the leakage current conduction mechanisms are also investigated as a function of thickness of Al2O3 passivation layer. The optimized interface state density extracted from the conductance method has reduced from $1.30 \times 10^{12}$ eV−1cm2 of Er2O3/InP to $7.27 \times 10^{11}$ eV−1cm2 of Er2O3/Al2O3/InP by adjusting the passivation layer thickness. As a result, it can be also confirmed that the passivation treatment is beneficial to inhibit the element’s diffusion and optimize the interface quality, significantly controlling the capacitor degradation caused by the leakage current through the stacked oxide layer.

In this letter, we present a novel analysis and design approach of self-oscillation frequency (SOF) for 0.8- ${{\mu }}\text{m}$ indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) emitter-coupled logic (ECL) and current-mode logic (CML) static frequency dividers. SOF of ECL and CML dividers is designed to be the maximum value after theoretical analysis and multiparameter optimization. The results show that the SOF of the ECL and CML divider is 62 and 37.5 GHz, respectively. With sinusoidal waveform input, the operating frequency range of the ECL divider is from 0.1 to 65 GHz, and CML is from 0.1 to 55 GHz, while the cut-off frequency ${f_{T}}$ is 150 GHz. For ECL, the ${f_{T}}$ utilization of SOF (SOF ${/}{f_{T}}$ ) is 0.413, and CML is 0.25. These are the maximum SOF results that can be designed for the two dividers under the same design conditions.

DC performances of depletion-mode 100 nm In0.53Ga0.47As/InP high electron mobility transistor (HEMT) heterogeneously integrated to silicon substrate by SiO2–SiO2 bonding were investigated by using numerical simulation. Effects of fixed charges at the InP/SiO2 interface, the SiO2/SiO2 bonding interface, and the SiO2/Si interface on HEMT are compared. Among these charges, dc characteristics of HEMT are most sensitive to fixed charges at the InP/SiO2 interface. With the density of negative fixed charges at the InP/SiO2 interface increasing from $\boldsymbol - 5\times 10^{{{10}}}$ to $\boldsymbol - 1\times 10^{{12}}$ cm−2, the energy band exhibits an upward bending and leads to a decrease of electron concentration in the channel. The threshold voltage shifts from −1.03 to −0.85 V and the output current exhibits a decrease of 96 mA/mm under the gate bias of 0 V; meanwhile, the breakdown voltage increases from 4.4 to 6.5 V under the gate bias of −1.6 V. A shift of ${C}$ – ${V}$ curves in pace with transfer characteristic curves further confirms that the two-dimensional electron gas (2DEG) channel of HEMT is indeed influenced by fixed charges at the InP/SiO2 interface. As a comparison, the other two charges exhibit a relatively weak influence, where the increase of charges at the SiO2/SiO2 bonding interface results in a 36 mV shift of threshold voltage and 20 mA/mm decrease of output current, and the charges at the SiO2/Si interface only cause 6 mV shift of threshold that can almost be ignored. We proposed an appropriate increase of InP layer thickness to mitigate the impact of fixed charges on the transfer and output characteristic of HEMTs.

We report uniform Type-II GaInAsSb/InP UTC-PDs, and compare their performance to devices fabricated with GaAsSb uniform and graded (composition and doping) absorbers of the same thickness. The quaternary UTC-PDs show a transit limited bandwidth of 274 GHz in contrast to 107 and 185 GHz for uniform and graded GaAsSb absorber UTC-PDs. Because the uniform quaternary and ternary UTC-PDs only differ in their absorber material, the findings conclusively demonstrate enhanced transport in GaInAsSb. Performance comparison to GaInAs-based devices from the literature suggest that GaInAsSb is a superior absorber material for λ = 1.55 μm high-speed photodetectors. Additionally, the external responsivity of the GaInAsSb UTC-PDs (0.094 A/W) is ~34% higher than the GaAsSb PDs (0.070 A/W). This is the first demonstration of a quaternary GaInAsSb absorber in UTC-PDs., Journal of Lightwave Technology, 39 (7), ISSN:0733-8724, ISSN:1558-2213

Single photon avalanche diodes (SPADs) are key enabling technologies for a wide range of applications in the near-infrared wavelength range. Recently, AlAs0.56 Sb0.44 (hereafter AlAsSb) lattice-matched to InP has been demonstrated for extremely low excess noise avalanche photodiodes (APDs) due to its large disparity between electron and hole ionization coefficients ( $\alpha $ and $\beta $ respectively). The $\alpha /\beta $ ratio also plays a role in Geiger mode operation as it affects the avalanche breakdown probability and hence detection efficiency. In this work, we theoretically investigate the performance of AlAsSb based SPADs. The probability of breakdown for electron-initiated Geiger mode operation increases more sharply with multiplication region width due to progressively more dissimilar ionization coefficients. In comparison with other common avalanche materials, such as InAlAs, InP and Si, our result also suggests that SPADs based on AlAsSb have a sharper breakdown probability than the other three materials under similar low overbias ratio. The calculated breakdown probability of 0.81 in AlAsSb is 0.18 and 0.28 higher than that of InAlAs/Si and InP respectively at 5% overbias ratio and with avalanche region width of 1500 nm.

Using quantum dot (QD) structures as active material for optoelectronics was already in focus before the development of quantum well (QW) lasers and before semiconductor lasers occupied an important place in the market. The big step in reducing laser threshold conditions by substituting bulk gain materials with QWs should find a logical continuation by further reducing the dimensionality toward full 3D carrier confinement by QDs. This was predicted by theoretical considerations at the beginning of the 1980s [1], [2]. However, no practical technologies were available at that time. Top-down approaches, as originally addressed, to produce nanoscale species on very large surfaces and interface areas resulted in the accumulation of a large defect density within the active region and the domination of nonradiative carrier recombination mechanisms. Only during the early 1990s was a major breakthrough achieved with the introduction of the bottom-up approach of strain-driven, self-organized epitaxial QD growth. The first lasers were obtained in the gallium arsenide (GaAs)-based material system [3].

Epitaxially integrating III-V lasers with Si-photonics is the key for compact, efficient, and scalable photonic integrated circuits (PICs). Here we present an investigation of a path forward in integrating III-V functionalities on industry-standard silicon-on-insulator (SOI) platforms using selective area hetero-epitaxy. Based on our recently developed methods of selectively growing device quality InP on (001)-oriented SOI wafers, we demonstrated InP stripes and segments, with dimensions varying from a few hundred nanometers to a few micrometers. The flexible epitaxy of InP on SOI together with the unique “bufferless” trait will enable efficient light interfacing with Si-based photonic devices using either evanescent or butt coupling schemes. We simulated the possibility of employing the micrometer-scale InP on insulator to realize electrically driven lasers and found that the metal induced optical loss is negligible when the InP dimension exceeds 4.0 μm. The potential of utilizing this selective area growth method to realize fully integrated Si-photonics is illustrated.

In this work we report the results of high density multi-channel optical multiprobes with pitches of 25 ${\mu }\rm{m}$ and 50 ${\mu }\rm{m}$ that provide edge-coupling used for on-wafer parallel testing of photonic integrated circuits. The probes are fabricated in an oxynitride platform and test demonstrations were carried out of edge-coupled indium-phosphide based photonic integrated circuits (PICs). Thirty-two optical parallel connections are simultaneously, passively aligned between the probe and the PIC by means of integrated guiding channels. The initial placement tolerance is more than 4 ${\mu }\rm{m}$ to give a passive alignment with an optical power variation of less than 1 dB. Multi-port loop-back optical power measurements are reported and the wavelength-dependent net modal gain of integrated semiconductor optical amplifiers was measured to further validate the concept.

We present a characterization method for polarization converters which improves the accuracy of traditional characterization methods significantly. An experimental demonstration of the method is presented on the InP-membrane-on-silicon (IMOS) platform. The design and fabrication of the polarization converter is discussed, as well as the simulated polarization conversion efficiency. A device of only 4 microns is shown to achieve 97.5%±0.5% polarization conversion, corresponding to an extinction ratio of -16± 0.9 dB. The traditional characterization method is compared to the new 4-port method, and the accuracy is improved from up to 20% to 0.5%.

The investigation on the effect of illumination power intensities for a thermophotovoltaic (TPV) system is crucial to enhance the TPV cell performance. To date, the studies on the effect of illumination intensities were limited to solar photovoltaic cells application. Meanwhile, the reported work on the impact of infrared illumination intensities on TPV cells are done at limited temperatures and intensities. The effects of TPV intensities on all performance parameters are not comprehensively studied and fully elucidated. Therefore, this paper investigates the performance of indirect-bandgap Germanium (Ge) and direct-bandgap Indium Gallium Arsenide (InGaAs) cells under various TPV spectral irradiances. Silvaco TCAD simulation software was used to investigate the effect of blackbody temperatures ranging from 800 to 2000 K with different illumination intensities on the TPV cell performances. It was found that higher conversion efficiencies are achieved for both TPV cells under higher illumination intensities due to the increase in open-circuit voltage and fill factor. As the beam intensity increases for temperatures >1600 K, fill factor slowly increases for the Ge cell, but decreases for the InGaAs cell due to the increase in the I2Rs losses associated with the high current. The finding demonstrates that the open-circuit voltage of indirect-bandgap TPV cell is significantly increased with higher illumination intensities. The variations in cells performance are explicitly explained based on factors such as TPV design structure and the physical properties of semiconductor at varying illumination intensities. The performance of both TPV cells were also analyzed at the minimum optical losses. Average efficiencies of Ge and InGaAs TPV cells were increased to 26.05% and 27.92%, respectively, when the optical losses were minimized with anti-reflection coating and thicker absorber layer. The results of this work demonstrate that by detailed consideration of the effect of spectral irradiances, a high-performance TPV system can be developed.

This article reports a detailed approach toward optimization of on-wafer thru-reflect-line (TRL) calibration structures for submillimeter-wave characterization of a state-of-the-art indium-phosphide (InP) technology, validated by thorough experimentation and electromagnetic (EM) simulation. The limitations of the existing RF test structures for high-frequency measurements beyond 110 GHz are analyzed through EM simulation. Using an optimization procedure based on calibration of raw EM simulated data, on-wafer TRL calibration structures were developed and fabricated in a subsequent run of this technology. Measurements could be achieved up to 500 GHz on the passive devices and up to 330 GHz on the InP double heterojunction bipolar transistors (DHBTs). The transistor measurements were validated by comparison with the HiCuM compact model simulation to 330 GHz for the InP DHBTs.

Most recently, III–V based ultrathin solar cells have attracted considerable attention for their inherent advantages, such as increased tolerance to defect recombination, efficient charge carrier separation, photon recycling, flexibility, and reduced material consumption. However, so far, almost all reported devices make use of conventional doped p-i-n kind of structures with a wide-bandgap III–V lattice-matched epitaxial window layer, for passivation and reduced contact recombination. Here, we show that a high-efficiency device can be obtained utilizing an InP thin film of thickness as low as 280 nm, without the requirement of a conventional p-n homojunction or epitaxial window layer. This is achieved by utilizing a wide-bandgap electron and hole selective contacts for electrons and holes transport, respectively. Under ideal conditions [assuming interface recombination velocity (IRV) = 103 cm/s and bulk lifetime = 1 μs], the proposed solar cell structure can achieve efficiency as high as 28%. Although, in the presence of bulk and interface Shockley–Read–Hall recombination, the efficiency reduces, still for bulk minority carrier lifetime as low as 2 ns and an IRV as high as 105 cm/s, an efficiency of ∼22% can be achieved with InP thickness as low as 280 nm. The proposed device structure will be beneficial in cases where the growth of controlled p-n homojunction and window layer can be tedious as in case of low-cost deposition techniques, such as thin-film vapour–liquid–solid and close-spaced vapour transport.

This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: an SSDA MMIC with 7.1dB average gain and 200GHz bandwidth; and the world’s first M-SSDA, which has a 12dB average gain and 170GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date.

This article describes the design and performance of a 140-GHz SiGe and a 100-GHz InP triple-stacked HBT distributed amplifier with active bias terminations. The active bias network is configured to extend the practical low-frequency operation while maintaining gain flatness and linearity. Triple-stacked HBTs are used to increase the gain–bandwidth and linear output capability. The SiGe design is based on HBTs with a peak $f_{\mathrm {T}}/f_{\mathrm {max}}$ of 300/350 GHz and achieves 11.7 dB of gain and a bandwidth from baseband to 140 GHz. The InP HBT design is based on DHBTs with a peak $f_{\mathrm {T}}/f_{\mathrm {max}}$ of 250/250 GHz and obtains a gain of 10.8 dB and a bandwidth of 100 GHz. Although the SiGe design achieves 1.5 times higher gain–bandwidth, the InP DHBT design achieves ~3–4.5 dB greater IP3, $P_{\mathrm {1~dB}}$ , and $P_{\mathrm {3 ~dB}}$ while consuming only ~23% higher dc power. These results represent the first broadband performance comparison of near-identical (apples–apples) DA designs implemented in SiGe and InP HBT device technologies. Although there are previous reports of larger bandwidth distributed amplifiers in both InP and SiGe technologies demonstrated up through 200 GHz, the InP and SiGe monolithic microwave integrated circuits (MMICs) described in this article are believed to represent the highest bandwidths reported for HBT DAs using practical on-chip active bias terminations.

The use of epitaxial regrowth of InP on lattice-matched In0.53Ga0.47 As for passivation of photodiodes lateral mesa surfaces is investigated. The effect of the regrown layer was examined by photoluminescence and dark current measurements and compared with results obtained with SiO2 and Al2O3 passivation layers. The integrated intensity of steady-state photoluminescence of InGaAs covered by InP increased by a factor between 15.5 and 58.9, depending on the excitation wavelength, denoting a strong reduction of nonradiative recombination. This reduction is expected to be the result of a strong reduction of intragap surface states. For the same photoluminescence measurements, both SiO2 and Al2O3 oxide passivation instead showed a reduction of the photoluminescence intensity. The dark currents of p-i-n photodiodes showed less striking results, a fact that we claim, probably is related to residual doping of the InP regrown layer.

Among the III-V semiconductor materials, indium arsenide (InAs) nanowire (NWs) with high carrier mobility are expected to be alternative channels for high-performance and low-power field-effect transistors (FETs). However, there is a challenge in enhancing the on-state current for the InAs NW-channel vertical gate-all-around (VGAA) structures on Si. We investigated vertical InAs/InP core-shell (CS) NW-channels to enhance the current and demonstrated InAs/InP CS NW VGAA FETs. The InAs/InP CS NW-channel enhanced the on-state current while maintaining a small off-leakage current. The devices showed an on-state current of 40 $\mu \text{A}/\mu \text{m}$ , off-leakage current of 1 pA/ $\mu \text{m}$ , and subthreshold slope of 111 mV/dec at $\text{V}_{\text {DS}} =0.50$ V. The origin of the current enhancement suggests that there is a formation of two-dimensional electron gas (2DEG) in the InAs/InP CS NW-channel, and the characteristics of the InAs/InP CS NW VGAA FET revealed that the InP interlayer at draian edge and low source resistivity are important parameters to take advantage of 2DEG for CS NW VGAA FET.

We present a novel photonic integrated circuit (PIC) that monolithically integrates a racetrack colliding-pulse mode-locked laser with a pulse-picking electro-absorption modulator and a semiconductor optical amplifier on Indium Phosphide. We present detailed characterization of this PIC that includes optical pulse characterization, phase noise and long term stability under passive and hybrid mode-locking conditions. Allan deviation measurements made on the optical pulse train from the PIC show a fractional frequency instability of $8\times 10 ^{-11}$ at 1 second and follow a 1/ $\tau $ trend. We also demonstrate repetition rate reduction from ~10 GHz to ~500 MHz with an extinction ratio of ~14.65 dB using an on-chip pulse-picking electro-absorption modulator.

In this article, for the first time, a hybrid plasmonic (HP) ring resonator uni-traveling carrier pin-photodetector was numerically presented that offers a high responsivity of 0.68 A/W, a high bandwidth of over 125 GHz, and low footprint. This device has the capability of monolithic integration with HP-passive devices on the InP platform at an optical communication wavelength of 1550 nm.

A 300-GHz quadrature voltage-controlled oscillator (QVCO) integrated with a pair of mixers based on an InP heterojunction bipolar transistor (HBT) technology has been developed. A super-harmonic coupling technique was applied to generate the quadrature signal in the QVCO. The oscillation frequency tuning range is 24.8 GHz (from 286.1 to 310.9 GHz), and the frequency range maintaining the quadrature operation (within ±10°) is 4.8 GHz (297.2–302.0 GHz). The maximum output power of the QVCO was measured as 0.46 dBm at 286.3 GHz. The measured phase noise is −91.4 dBc/Hz with 10 MHz offset at 294.2 GHz. The integrated QVCO-mixer consumes a dc power of 167.5 mW.

This paper reports on a 100-nm gate length InP high-electron-mobility transistor (HEMT) technology for cryogenic low-noise amplifiers (LNAs) with ultra-low power dissipation of $112~\mu \text{W}$ . This result was obtained by using 100-nm gate length InP HEMTs with improved transconductance at low drain current through a scaled-down gate-channel distance while maintaining a low gate leakage current with the use of an InP etch stop layer and Pt gate metal. The noise performance of InP HEMTs was demonstrated in a 4–8 GHz (C–band) three-stage hybrid LNA at the ambient temperature of 5 K. At a dc power dissipation of $300~\mu \text{W}$ , the average noise temperature was 2.8 K with 27 dB gain. At a dc power dissipation of $112~\mu \text{W}$ , the LNA exhibited an average noise temperature of 4.1 K with a gain of 20 dB. The presented results demonstrate the large potential of InP HEMT technology for sub-mW cryogenic LNA design.

We design a lossless $8 \times 8$ Silicon Photonics (SiPh)/Indium Phosphide (InP) hybrid optical switch. The design consists of an 8-channel InP gain block for coupling to an $8 \times 8$ thermally tuned Mach-Zehnder interferometer-based Banyan switch in a passive SiPh platform. The gain block is an array of eight $1300~\mu \text{m}$ -long semiconductor optical amplifiers (SOAs). We experimentally verified the InP gain block while the SiPh chip is accounted by replacing it with a loss component. The SOA in line with the optical signal path provides a net gain larger than 25 dB to compensate for the inherently large insertion loss of the $8 \times 8$ SiPh optical switch. The total energy consumption of the hybrid optical switch in lossless operation mode is 10.44 pJ/bit at 12.5 Gb/s.

A wideband monolithic microwave/millimeter-wave integrated circuit (MMIC) distributed amplifier (DA) using a 3-D interdigital capacitor at the input of the gain cell is demonstrated in an indium phosphide (InP) heterojunction bipolar transistor (HBT) process. The proposed DA using interdigital capacitors improves the input return loss at high frequencies compared with the one implemented with conventional metal–insulator–metal (MIM) capacitors. The fabricated amplifier achieves a measured average gain of 10.5 dB over a 3-dB bandwidth from 1 to 160 GHz. The maximum measured saturated power ( $P_{\mathrm {sat}}$ ) is 17.8 dBm with the corresponding 1-dB compression power ( $P_{\mathrm {1\,dB}}$ ) of 15 dBm at 55 GHz. The amplifier achieves a minimum $P_{\mathrm {sat}}$ of 14.6 dBm up to 110 GHz.

We fabricated InGaP/GaAsSb/InGaAsSb/InP double heterojunction bipolar transistors (DHBTs) with an aggressive lateral and vertical scaling technology to improve the current gain cutoff frequency ( ${f}_{\text {t}}$ ) further. A 13-nm-thick GaAsSb/InGaAsSb base and a 40-nm-thick InP collector are used to reduce electron transit time. In addition, the width of the base electrode on each side of the emitter is reduced to about 0.05 $\mu \text{m}$ to suppress increases in parasitic collector capacitance. A fabricated DHBT with the emitter size of 0.24 $\mu \text{m}\,\,\times7.8\,\,\mu \text{m}$ exhibits maximum differential current gain of ~95 and collector-emitter breakdown voltage of 2.6 V. At a collector current density of 18 mA/ $\mu \text{m}^{{2}}$ , the DHBT exhibits ${f}_{\text {t}}$ of 813 GHz, which is the highest among all types of transistors measured at a room temperature.

We report on the free-running and frequency stabilized operation of a ring resonator-tuned full-band tuneable laser. The laser is a monolithically integrated semiconductor ring laser tuneable over 34 nm, from 1522-1556 nm, fabricated using a commercially-available, InP-based, active-passive foundry technology. The mode selection is implemented using the Vernier effect by reverse-biasing voltage-controlled electro-optically tuned ring resonators. The laser exhibits a typical intrinsic linewidth of 110 kHz over the C-band and a side-mode suppression ratio (SMSR) exceeding 50 dB. The linewidth over the tuning range does not significantly vary, showing that the tuning mechanism does not cause linewidth broadening. The power dissipated in the tuning elements is 1.4 mW per ring. Using the same reverse bias voltage-controlled electro-optic tuning, we also demonstrate the locking of the laser to a high-finesse etalon using Poun-Drever-Hall frequency locking. Our implementation requires a single control loop because of the reverse bias tuning. All deployed tuning effects in the phase modulators have the same sign therefore resulting in a flatter frequency dependent phase response compared to current injection feedback. The control loop has a bandwidth of 500 kHz and a control range of 2.9 GHz. We report 1 kHz level linewidth for millisecond observation times for the stabilized laser.

Avalanche photodiodes (APDs), and single photon avalanche diodes (SPADs), with InP avalanche regions and InGaAs absorption regions, are used for detecting weak infrared light at ∼1.55 μm wavelength. These devices are often cooled to below room temperature during operation yet both validated simulation models and impact ionization coefficients that accurately describe the avalanche characteristics of InP are lacking in the temperature range of interest (200 K to room temperature). In this article we present an accessible, validated temperature dependent simulation model for InP APDs/SPADs. The model is capable of simulating avalanche gain, excess noise, breakdown voltage, and impulse current at 150–300 K. Temperature dependent ionization coefficients in InP, which may be used with other APD/SPAD simulation models, are also presented. The data reported in this article is available from the ORDA digital repository (DOI: 10.15131/shef.data.c.4373006).

A vertical bi-stable resistor (biristor) composed of In0.53Ga0.47As was demonstrated for sub-1 V operation. An inherent small bandgap and a scaled base length of 150 nm led to the remarkable reduction in latch-up voltage compared to Si(Ge)-based conventional biristors. The epitaxially grown n-p-n structure allowed an abrupt p-n junction, which was also very important to reduce the latch-up voltage. Furthermore, the physical mechanism of carrier transport in the InGaAs biristor was explored with TCAD simulations.

In this work, two novel virtual user association and resource allocation algorithms are introduced for a wireless virtualized heterogeneous network with hybrid energy supply. In the considered system, macro base stations (MBSs) are supplied by the grid power and small base stations (SBSs) have the energy harvesting capability in addition to the grid power supplement. Multiple infrastructure providers (InPs) own the physical resources, i.e., BSs and radio resources. The Mobile Virtual Network Operators (MVNOs) are able to recent these resources from the InPs and operate the virtualized resources for providing services to different users. In particular, aiming to maximize the overall utility for the MVNOs, a joint resource (spectrum and power) allocation and user association problem is presented. First, we present an alternating direction method of multipliers (ADMM)-based algorithm solution to find the near-optimal solution in a static manner. Moreover, we also utilize deep reinforcement learning to design the optimal policy without knowing a priori knowledge of the dynamic nature of networks. We have conducted extensive simulation and the performance evaluation demonstrate the advantages and effectiveness of the proposed schemes. peerReviewed

Photonic neuromorphic computing is raising a growing interest as it promises to provide massive parallelism and low power consumption. In this paper, we demonstrate for the first time a feed-forward neural network via an 8 × 8 Indium Phosphide cross-connect chip, where up to 8 on-chip weighted addition circuits are co-integrated, based on semiconductor optical amplifier technology. We perform the weight calibration per neuron, resulting in a normalized root mean square error smaller than 0.08 and a best case dynamic range of 27 dB. The 4 input to 1 output weighted addition operation is executed on-chip and is part of a neuron, whose non-linear function is implemented via software. A three feedback loop optimization procedure is demonstrated to enable an output neuron accuracy improvement of up to 55%. The exploitation of this technology as neural network is evaluated by implementing a trained 3-layer photonic deep neural network to solve the Iris flower classification problem. Prediction accuracy of 85.8% is achieved, with respect to the 95% accuracy obtained via a computer. A comprehensive analysis of the error evolution in our system reveals that the electrical/optical conversions dominate the error contribution, which suggests that an all optical approach is preferable for future neuromorphic computing hardware design.

We present waveguide photonic crystal reflectors on the InP-membrane-on-silicon (IMOS) platform, and a method to accurately measure the reflectivity of those reflectors. The photonic crystal holes are patterned on a waveguide using electron-beam lithography and etched through the waveguiding layer to create a broadband distributed Bragg reflector. We show simulations of these reflectors and experimental results of fabricated devices, both showing a high, free-to-choose reflectivity, and high quality factor Fabry-Pérot cavities. We experimentally show reflectivities higher than 95% for the reflectors and a quality factor as high as 15,911±511 for a Fabry-Pérot cavity, using reflectors with a length of only 4 microns. For the first time, to our knowledge, two methods for measuring the reflectivity are used for characterization of on-chip reflectors to accurately determine the reflection. The first method is based on analysis of the transmission through a Fabry-Pérot cavity, the second is based on a direct four-port measurement of the reflector. A systematic error is made in both methods, resulting in an upper and lower boundary for the actual reflection coefficient.

In this article, a 220-GHz direct detection polarimetric receiver is reported. This polarimetric receiver is intended for sensing of the microphysical properties of cloud ice in the earth’s upper atmosphere. In the article, we report the measured RF performance, including RF gain of approximately 35 dB per channel and integrated noise figure of the receiver. The noise figure is measured to be 5.1 dB for the horizontally polarized channel and 5.4 dB for the vertically polarized channel. The receiver measures only 1.8 cm $\times3.0$ cm $\times6.4$ cm and has a total regulated dc power consumption of 520 mW. This article represents the first 220-GHz polarimetric direct detection receiver and is enabled by an advanced 25-nm indium phosphide (InP) HEMT monolithic microwave integrated circuit (MMIC) technology.

Type-I (straddled) InP DHBT devices have been fabricated to study the impact of different base-collector junction transition layer designs on the collector to emitter breakdown behavior, breakdown voltage, BVceo and the device output performance such as knee voltage, Vknee at high collector current densities, Jc. An abrupt breakdown behavior with BVceo of 11V and Vknee less than 1V at Jc>100kA/cm2 are achieved using an optimized base collector junction transition layer design. Using 2D numerical simulations, components of leakages dominating Iceo at low and high collector to emitter bias voltages are explained. It is further shown that the optimized device exhibits good RF and power performance achieving f $_{T}$ of 115GHz and f $_{max}$ of 150GHz at emitter width >1um. An MMIC power amplifier (PA) is also designed and fabricated using the optimized Type-I InP DHBT device. At 28GHz, good power performance is achieved with PAE of 54% and Psat of 26dBm. Thus, it is shown that InP DHBTs developed in this work are a good candidate for the next phase of 5G millimeter wave Ka-band power amplifier applications.

GaInAs/InAs composite channels in InP-based pHEMTs enable wideband and/or low-noise performances because of their superior carrier transport properties. To date, the influence of the InAs inset design details on transistor performance has not been parametrized in the literature. We present a systematic study of the effects of the InAs channel inset thickness on transistor characteristics and cutoff frequencies versus temperature, and on the noise performance at 300 K. The epitaxial layer structures considered here incorporate 2 to 5-nm InAs insets in a fixed total composite channel thickness. All layers exhibit excellent electron mobilities (from 40 200 to 54 800 cm2/Vs at 77 K). Thicker InAs insets improve both the current gain cutoff frequency ( ${f}_{\text {T}}$ ) and the maximum oscillation frequency ( ${f}_{\text {MAX}}$ ). However, they also result in higher gate leakage currents and increased channel impact ionization. 50-nm gate length pHEMTs with a 5-nm InAs inset feature the highest simultaneous ${f}_{\text {T}} / {f}_{\text {MAX}} \ge {390}$ /675 (455/800) GHz at 300 (15) K for a low-noise bias but exhibit the poorest minimum noise figure ${NF}_{\text {MIN}}$ . Whereas higher ${f}_{\text {T}}$ (and/or ${f}_{\text {MAX}}$ ) values have traditionally been associated with improved noise performances, this is no longer the case.

We report the broadband characterization of an indium phosphide monolithically integrated optical frequency comb generator based on cascaded modulators. The device consists of a dual-drive Mach–Zehnder modulator (MZM), two cascaded phase modulators, and is also equipped with an integrated laser source, resulting in an extremely compact device, tunable both in wavelength and comb line frequency. Comb generation is shown in the range 4 to 8 GHz, and comb line multiplication is demonstrated, for the first time in an integrated device, exploiting the dual-drive configuration of the MZM. In particular, by feeding the MZM upper and lower arms with two synchronous sinusoidal RF signals, where one signal frequency is multiple of the others. At the repetition rate of 1 GHz, this technique allows to obtain up to 55 comb lines within a 3 dB power variation. A characterization of the comb phase noise when line multiplication is performed is also reported.

Indium phosphide (InP) is the most developed platform for photonic integrated circuits (PICs). Of interest is the advancement of this platform for applications that demand high performance, especially high output power, including free space communications and microwave photonics. In this paper, we summarize development of InP-based PIC transmitters. Two transmitter types were fabricated: one based on an offset quantum wells (OQW) platform and the other on a quantum well intermixing (QWI) platform. The OQW-based transmitter consists of a widely tunable laser, a high-speed semiconductor optical amplifier (SOA), a Mach–Zehnder modulator, and an output SOA. This transmitter demonstrates a 44-nm tuning range, >45 dB side mode suppression ratio, 14.5 dBm off -chip power, and a data rate of 7 Gbps. The second transmitter, based on QWI, utilizes an alternate epitaxial structure to achieve a lower confinement factor for higher SOA output saturation power. This QWI transmitter consists of a distributed Bragg reflector laser, a high-speed SOA, an electroabsorption modulator, and an output SOA. The measured off -chip power is 19.5 dBm, and a data rate of 20 Gbps is demonstrated. Based on the improved performance with the new epitaxial structure, a novel platform for high-power PIC transmitters integrated with low confinement and high-power SOAs is described.