79 results on '"Kim, Tony"'
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2. A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based TEXPRESERVE0 ADC Suitable for DVFS
3. A 1Mb RRAM Macro With 9.8ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation
4. HGRP: A 181-$\mu$W Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free Feature Clustering
5. A Reconfigurable Step-Down Switched-Capacitor Power Converter Using Optimized Partial Series-Parallel (OPSP) Topology
6. BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
7. A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN
8. A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process
9. A Reconfigurable CMOS Ising Machine with Three-Body Spin Interactions for Solving Boolean Satisfiability with Direct Mapping
10. Transposable 9T-SRAM Computation-In-Memory for On-Chip Learning with Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices
11. A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory
12. A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks
13. A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration
14. A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation
15. A Time-Domain Wavefront Computing Accelerator With a 32 $\times$ 32 Reconfigurable PE Array
16. A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
17. A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications
18. A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
19. A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices
20. An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning
21. Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits
22. A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices
23. Guest Editorial Special Issue on Selected Papers From ISCAS 2021
24. A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI
25. A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS
26. Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks
27. A Capacitance to Digital Converter Using Continuous Time ΔΣ Modulator for Microphone-Based Auscultation
28. A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection
29. A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks
30. A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications
31. A High Reliable SRAM-Based PUF with Enhanced Challenge-Response Space
32. Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory
33. Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding
34. Development of a Handheld Volumetric Photoacoustic Imaging System With a Central-Holed 2D Matrix Aperture
35. A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices
36. A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines
37. SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction
38. A 0.5 V 8–12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations
39. A Secure Data-Toggling SRAM for Confidential Data Protection
40. A 213.7-$\mu$ W Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm
41. An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI
42. IEEE SSCS Singapore Chapter Hosts DL Prof. Jae-Yoon Sim [Chapters]
43. An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With$0.175~\mu$W/Channel in 65-nm CMOS
44. A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver
45. A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC–DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme
46. An 88% Efficiency 0.1–300- $\mu$W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes
47. A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS
48. An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators
49. An Area and Energy Efficient Ultra-Low Voltage Level Shifter With Pass Transistor and Reduced-Swing Output Buffer in 65-nm CMOS
50. A Self-Adaptive Time-Based MPPT With 96.2% Tracking Efficiency and a Wide Tracking Range of 10 $\mu$ A to 1 mA for IoT Applications
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