40 results on '"Kranti, Abhinav"'
Search Results
2. Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics
3. Incorporating Quantum Effects in Ultralow Power (ULP) Subthreshold Logic Design With Junctionless Nanowire Transistor
4. An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET
5. Improved Mobility Extraction Methodology for Reconfigurable Transistors Considering Resistive Components and Effective Drain Bias
6. Limits on Hysteresis-Free Sub-60 mV/Decade Operation of MFIS Nanowire Transistor
7. Bi-Directional Junctionless Transistor for Logic and Memory Applications
8. Gate-All-Around Nanowire Junctionless Transistor-Based Hydrogen Gas Sensor
9. Relevance of Device Cross Section to Overcome Boltzmann Switching Limit in 3-D Junctionless Transistor
10. 1T-DRAM With Shell-Doped Architecture
11. Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact
12. Modeling Short-Channel Effects in Core–Shell Junctionless MOSFET
13. Overcoming Biomolecule Location-Dependent Sensitivity Degradation Through Point and Line Tunneling in Dielectric Modulated Biosensors
14. Modeling Short-Channel Effects in Asymmetric Junctionless MOSFETs With Underlap
15. Regaining Switching by Overcoming Single-Transistor Latch in Ge Junctionless MOSFETs
16. Role of Surface States and Interface Charges in 2DEG in Sputtered ZnO Heterostructures
17. High Retention With${n}$-Oxide- ${p}$Junctionless Architecture for 1T DRAM
18. Enhanced Sheet Charge Density in DIBS Grown CdO Alloyed ZnO Buffer Based Heterostructure
19. Raised Source/Drain Germanium Junctionless MOSFET for Subthermal OFF-to-ON Transition
20. Dielectric Modulated Biosensor Architecture: Tunneling or Accumulation Based Transistor?
21. Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM
22. A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET
23. Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application
24. Analytical Model for 2DEG Density in Graded MgZnO/ZnO Heterostructures With Cap Layer
25. Steep-Switching Germanium Junctionless MOSFET With Reduced OFF-State Tunneling
26. Variation of Threshold Voltage With Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs
27. Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM
28. Buffer Layer Engineering for High ( $\geq 10^{\mathrm {13}}$ cm $^{\mathrm {-2}}$ ) 2-DEG Density in ZnO-Based Heterostructures
29. Applicability of Transconductance-to-Current Ratio ( $g_{\mathrm {m}}/I_{\mathrm {ds}}$ ) as a Sensing Metric for Tunnel FET Biosensors
30. A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage
31. Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism
32. Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications
33. High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications
34. Device Design and Estimated Performance for p-Type Junctionless Transistors on Bulk Germanium Substrates
35. Junctionless Multiple-Gate Transistors for Analog Applications
36. Influence of Elastic and Inelastic Electron–Phonon Interaction on Quantum Transport in Multigate Silicon Nanowire MOSFETs
37. Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off
38. High Tolerance to Gate Misalignment in Low Voltage Gate-Underlap Double Gate MOSFETs
39. Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications
40. Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.