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This paper proposed LightSleepNet -a light-weight, 1-d Convolutional Neural Network (CNN) based personalized architecture for real-time sleep staging, which can be implemented on various mobile platforms with limited hardware resources. The proposed architecture only requires an input of 30s single-channel EEG signal for the classification. Two residual blocks consisting of group 1-d convolution are used instead of the traditional convolution layers to remove the redundancy in the CNN. Channel shuffles are inserted into each convolution layer to improve the accuracy. In order to avoid over-fitting to the training set, a Global Average Pooling (GAP) layer is used to replace the fully connected layer, which further reduces the total number of the model parameters significantly. A personalized algorithm combining Adaptive Batch Normalization (AdaBN) and gradient re-weighting is proposed for unsupervised domain adaptation. A higher priority is given to examples that are easy to transfer to the new subject, and the algorithm could be personalized for new subjects without re-training. Experimental results show a state-of-the-art overall accuracy of 83.8% with only 45.76 Million Floating-point Operations per Second (MFLOPs) computation and 43.08 K parameters.

This paper proposed a wearable smart sEMG recorder integrated gradient boosting decision tree (GBDT) based hand gesture recognition. A hydrogel-silica gel based flexible surface electrode band is used as the tissue interface. The sEMG signal is collected using a neural signal acquisition analog front end (AFE) chip. A quantitative analysis method is proposed to balance the algorithm complexity and recognition accuracy. A parallel GBDT implementation is proposed featuring a low latency. The proposed GBDT based neural signal processing unit (NSPU) is implemented on an FPGA near the AFE. A RF module is used for wireless communication. A hand gesture set including 12 gestures is designed for human-computer interaction. Experimental results show an overall hand gesture recognition accuracy of 91%.

This paper proposed the design of a low-noise, low total harmonic distortion (THD) chopper amplifier for neural signal acquisition. A dc servo loop (DSL) based on active Gm-C integrator is proposed to reject the electrode-dc-offset (EDO). Architecture of a complementary input very low-transconductance (VLT) operational transconductance amplifier (OTA) was proposed and integrated in the active Gm-C integrator to improve the linearity as well as to reduce the noise, featuring a transconductance ranging from 45 pS to a few nS. The proposed amplifier was fabricated in a TSMC 0.18- $\mu \text{m}$ CMOS process, occupying an area of 0.2 mm 2, featuring a power consumption of $3.24~\mu \text{W}$ /channel under a 1.8-V supply voltage. The THD for a 5-mVpp input is lower than −61 dB. An input-referred thermal noise power spectral density (PSD) of 39 nV/ $\sqrt {\text {Hz}}$ is measured. The measured input-referred noise is $0.65~\mu \text {V}_{\text {rms}}$ in the 0.3–200-Hz frequency band and $2.14~\mu \text{V}_{\text {rms}}$ in the 200-Hz–5-kHz frequency band, respectively, leading to a noise-efficiency factor of 2.37 (0.3–200 Hz) and 1.56 (0.2 k–5 kHz). In addition, the high-pass corner frequency can be precisely configured and linearly adjusted with the external bias current from 0.35 to 54.5 Hz.

Presents information on the Symposium on Bio-Inspired Circuits 2017: Past, Present, and Future Outlook.

This brief presents a wireless, low-power embedded system that recognizes hand gestures by decoding surface electromyography (EMG) signals. Ten hand gestures used on commercial trackpads, including pinch, stretch, swipe left, swipe right, scroll up, scroll down, single click, double click, pat, and ok, can be recognized in real time. Features from four differential EMG channels are extracted in multiple time windows. Unlike traditional data segmentation methods, an event-driven method is proposed, with the gesture event detected in the hardware. Feature extraction is triggered only when an event is detected, minimizing computation, memory, and system power. A time-delayed artificial neural network (ANN) is used to predict the gesture from the transient EMG features instead of traditional steady-state features. The ANN is implemented in the microcontroller with a processing time less than 0.2 ms. The detection results are sent wirelessly to a computer. The device weights 15.2 g. A 4.6 g battery supports up to 40 h continuous operation. To our knowledge, this brief shows the first real-time, embedded hand-gesture-recognition system using only transient EMG signals. Experiments with four subjects show that the device can achieve a recognition of ten gestures with an average accuracy of 94%.

Reliable, multi-channel neural recording is critical to the neuroscience research and clinical treatment. However, most hardware development of fully integrated, multi-channel wireless neural recorders to-date, is still in the proof-of-concept stage. To be ready for practical use, the trade-offs between performance, power consumption, device size, robustness, and compatibility need to be carefully taken into account. This paper presents an optimized wireless compressed sensing neural signal recording system. The system takes advantages of both custom integrated circuits and universal compatible wireless solutions. The proposed system includes an implantable wireless system-on-chip (SoC) and an external wireless relay. The SoC integrates 16-channel low-noise neural amplifiers, programmable filters and gain stages, a SAR ADC, a real-time compressed sensing module, and a near field wireless power and data transmission link. The external relay integrates a 32 bit low-power microcontroller with Bluetooth 4.0 wireless module, a programming interface, and an inductive charging unit. The SoC achieves high signal recording quality with minimized power consumption, while reducing the risk of infection from through-skin connectors. The external relay maximizes the compatibility and programmability. The proposed compressed sensing module is highly configurable, featuring a SNDR of 9.78 dB with a compression ratio of 8×. The SoC has been fabricated in a 180 nm standard CMOS technology, occupying 2.1 mm $\times$ 0.6 mm silicon area. A pre-implantable system has been assembled to demonstrate the proposed paradigm. The developed system has been successfully used for long-term wireless neural recording in freely behaving rhesus monkey.

This paper describes a compressive acquisition image sensor realizing an on-chip focal plane compressive sensing algorithm. The proposed design enables signal sampling at a rate much lower than the Nyquist rate while preserving the capability to recover the useful information of the signal. Address events are employed to convert illumination intensity into time domain information, eliminating the use of analog-to-digital converters and effectively reducing the readout rate. A pixel-level all digital address event triggered compressive sensing request generator is implemented. An image pixel array of 48 $\times$ 72 was fabricated in 0.18 $\mu{\text{m}}$ standard CMOS technology, featuring a 22-transistor all-digital pixel architecture with a size of $15\times 15\ \mu{\text{m}}^{2}$ and a fill factor of 32.4%. Experimental results show a higher than 10 compression ratio with a power consumption of 1.56 mW at 23 fps under image acquisition mode.

In this paper, a bioinspired monolithic complementary metal-oxide-semiconductor (CMOS) polarization image sensor is described as a solution to real-time polarization image capture. Metallic wire-grid gratings are integrated onto standard CMOS image sensor arrays with different orientations. A numerical analysis is performed to guide the design of the wire-grid arrays. Experimental results from different CMOS processing units are compared. A current-mode polarization processing unit is designed, fabricated, and tested in order to perform the extraction of the polarization characteristics from the captured intensities. This paper illustrates how polarization image processing can be used to monitor live cells. Several polarization processing methods with different computational complexity and data requirements have been applied and compared.

In this paper, a low-power, multifunctional CMOS smart sensor node is designed for an electronic facade, which provides an alternative solution to the concept of energy-efficient responsive buildings. Various sensing capabilities, including light intensity sensing, temperature sensing, motion tracking, and compressive image acquisition, are implemented on the sensor node. An 80 × 80 image pixel array is employed for motion tracking and compressive image acquisition. Various operational modes are realized, including: 1) event generation mode; 2) motion tracking mode; and 3) video output mode in full-resolution or compressed by the region of interest (ROI). A low-power, high-throughput motion detection algorithm is proposed in this paper. The power consumption of the proposed work is modeled, analyzed, and compared with traditional motion detection methods. According to numerical analysis, the throughput can be increased by 45% while using the proposed design instead of traditional temporal differential motion tracking methods with simislar power consumption. The proposed algorithm is realized by a pixel-level focal-plane motion detection unit, consisting of switched-capacitor circuit, analog memory, and dual-threshold comparator. The proposed design was fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm 2 silicon area. The total power consumption is 17 μW, while the pixel array is performing motion tracking with a frame rate of 30 fps and a supply voltage of 3.3 V.

Current mode active pixel sensors convert light intensity into an analog output current. A current mode image sensor enables simple implementation of focal plane algebraic functions but suffers from poor linearity and large fixed-patten noise. This paper analyzes the causes of the non-linearity of a current-mode image sensor including a theoretical derivation and numerical simulation. Previously reported linearity improvement methods are reviewed, while an architecture of a current mode image sensor with a voltage feedback loop between pixel output and the current conveyor for linearity enhancement is proposed. An image sensor array of 100 $\times$ 200 current mode pixels is fabricated in a 0.5 $\mu{\rm m}$ 2P3M standard CMOS processing technology. Experimental results illustrate a 45% improvement of the linearity of the proposed imager. Fixed pattern noise is reduced by 57.6% for the maximum readout current, which can be further reduced by another 51.5% after gain calibration. A signal to noise ratio of 49.6 dB is achieved.

In this paper, we report on an image sensor with an integrated focal-plane 2 × 2 wire-grid polarizer for the visible spectrum, fabricated in a 65-nm standard CMOS technology. This imager enables the reconstruction of the polarization response for each pixel. Finite-difference time-domain method has been used to optimize the extinction ratio (ER) in the visible spectrum of a multilayered focal-plane wire-grid polarizer. Experimental results show that an ER of 16.35 dB is achieved with a standard error of ~ 0.25% between the experimental results and the fitting sinusoidal polarization response curve. Design guidelines for the wire-grid polarizer are derived based on numerical analysis and experimental results. Sensitivity ratio is defined to balance the tradeoff between the intensity sensitivity and polarization sensitivity of the imager.

The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed.

In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel.