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A configurable-bandwidth charge-domain filter (CDF) with bandwidth calibration and clock-pulse modulation (CPM) is proposed. The bandwidth calibration scheme controls the insertion loss at a pre-specified frequency by modulating the feedback gain and delay; this helps the CDF to suppress the sinc distortion and thus achieve near-ideal brick-wall filtering. For multi-frequency compensation, a multi-stage CDF architecture is utilized to organize the feedback delay. Together with non-decimation filtering, the noise folding effect as well as the chip area can be reduced. On the other hand, to provide a stable gain under variable channel bandwidth, a CPM scheme is proposed; it adjusts the clock period with a fixed pulse width by zero-insertion. Implemented in a 65-nm CMOS technology, the proposed CDF achieves 58.9-dB adjacent-channel rejection (ACR), 85.5-dB stop-band attenuation (SBA), 41-dB conversion gain, and 19.5-MHz channel bandwidth at 320-MS/s input-sampling rate. Furthermore, for input-sampling rates range from 300 to 480 MS/s, the channel bandwidth can be configured from 5 to 26 MHz. At 1.2-V supply, the chip consumes 8.4-mW power and occupies 0.52-mm2 area.

A quadrature charge-domain filter (QCDF) is proposed for downconversion and filters in RF receivers. The QCDF is designed with a chosen IF of 268 MHz, which is assumed a downconverted signal from 802.11 g RF signals by a subsampling or subharmonic mixer. Through a sampling rate of 1072 MS/s, the QCDF possessed 53-dB stopband attenuation, 32.51-dB alias-band attenuation, and 44-MHz bandwidth. For quadrature performance, this QCDF provided -27.67-dB error vector magnitude, using a 64 quadratic amplitude modulation signal with a bit rate of 54 Mb/s. This chip totally consumed 7.7 mA from a 1.2-V power supply and occupied 0.08 mm2 in 90-nm CMOS logical process.

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.