62 results on '"Okada, Kenichi"'
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2. A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation
3. A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter
4. A 256-Element Phased-Array Relay Transceiver for 5G Network Using 24-GHz Wireless Power Transfer With Discrete ICs
5. A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression
6. A D-Band Wideband Single-Ended Neutralized Up-Conversion Mixer with Controlled LO Feedthrough in 65nm CMOS
7. A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal
8. A 19–34-GHz Bridged-T Phase Shifter With High-Pass Phase Compensation Achieving 3.9∘ RMS Phase Error for 5G NR
9. A Low-Power 256-Element $Ka$-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations
10. 300-GHz-Band Four-Element CMOS-InP Hybrid Phased-Array Transmitter With 36$^{\circ}$ Steering Range
11. A $Ka$-Band 64-Element Deployable Active Phased-Array TX on a Flexible Hetero Segmented Liquid Crystal Polymer for Small Satellites
12. A Compact 28GHz Bi-Directional Power-Combined Antenna Interface in WLCSP for 5G and B5G Transceivers
13. A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049$^{\circ}$ and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD
14. A 39-GHz CMOS Bidirectional Doherty Phased-Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station
15. A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR
16. A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation
17. A 1-Bit-DSM-Based Digital Polar Power Amplifier Supporting 1024-QAM
18. A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer
19. A CMOS 24–30-GHz Low-Phase-Variation Variable Gain Amplifier Design for 5G New Radio
20. A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth
21. A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems
22. A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
23. A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch
24. A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
25. 300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers
26. A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS
27. Accurate Transistor Modeling by Three-Parameter Pad Model for Millimeter-Wave CMOS Circuit Design
28. A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS
29. A 28.16-Gb/s Area-Efficient 60-GHz CMOS Bidirectional Transceiver for IEEE 802.11ay
30. Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator
31. A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency-Locked Loop
32. A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
33. ULPAC: A Miniaturized Ultralow-Power Atomic Clock
34. A 273–301-GHz Amplifier With 21-dB Peak Gain in 65-nm Standard Bulk CMOS
35. A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio
36. A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS
37. A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios
38. A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD
39. A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS
40. A Sub-mW Fractional- ${N}$ADPLL With FOM of −246 dB for IoT Applications
41. Progressive Mixing Technique to Widen the Locking Range of High Division-Ratio Injection-Locked Frequency Dividers
42. A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c
43. A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications
44. 64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay
45. A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC
46. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
47. A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture
48. A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad
49. Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference
50. Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC)
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