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Chemical mechanical planarization (CMP) models which are able to make predictions for a full chip are highly desirable in semiconductor manufacturing. Previous models proposed to this end have largely focused on effects of pattern density. We here extend one of the proposals to include also effects of pattern-size based on a consideration of the roughness of the polishing pad. Experimental data from CMP test structures containing variations of both pattern-density and pattern-size are used to validate the model. The results are applied to both interlayer dielectric-CMP and shallow trench isolation-CMP as particularly important processes in industry.

For the first time, HfZrO4 dielectrics deposited with metal-organic chemical vapor deposition (MOCVD) as well as atomic layer deposition (ALD) have been investigated as high-k gate dielectric for 32-nm high-performance logic SOI complementary metal-oxide-semiconductor devices in this letter. The composition of the HfZrO4 films has been analyzed in detail by atom probe tomography, Rutherford backscattering spectrometry, and X-ray photoelectron spectroscopy. Optical inline measurements and electrical parameters such as gate leakage current, capacitance equivalent thickness, threshold voltage, and performance as well as reliability data have been taken into account to directly compare both deposition methods. All parameters indicate a comparable behavior for MOCVD and ALD. Therefore, MOCVD has been demonstrated to be a promising alternative to ALD in high-volume manufacturing.