14 results on '"Sakui, K."'
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2. Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
3. A source-line programming scheme for low-voltage operation NAND flash memories
4. A CMOS bandgap reference circuit with sub-1-V operation
5. A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories
6. A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology
7. Quick address detection of anomalous memory cells in a flash memory test structure
8. A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
9. The effects of impact ionization on the operation of neighboring devices and circuits
10. BiCMOS circuit technology for high-speed DRAMs
11. Noise-generation analysis and noise-suppression design techniques in megabit DRAMs
12. An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode
13. A high-performance 1-Mbit dynamic RAM with a folded capacitor cell
14. A new static memory cell based on the reverse base current effect of bipolar transistors
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