Search

The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s digitizer application-specific integrated circuit (ASIC) intended for use inside the DUNE Far Detector. ColdADC_P2 contains two 16 MS/s pipelined analog-to-digital converters (ADCs) that each digitizes the output of eight sample-and-hold amplifiers (SHAs). Because the application requires immersion in liquid argon (LAr), ColdADC_P2 was developed using specialized design techniques for long-term reliability in cryogenic environments and a customized cryogenic standard cell library. ColdADC_P2, with a die area of approximately 52.4 mm2 and fabricated in 65-nm CMOS technology, achieves 130- μ V rms noise performance and 11.8-bit effective-number-of-bits (ENOB) at a temperature of 77 K, with channel-to-channel crosstalk of < 0.06% while dissipating 338 mW (21 mW per channel). Residual nonlinearity that is consistent with dielectric absorption in the capacitors internal to the ADC is corrected using a lookup table.

Power electronics switching devices made on wide-bandgap (WBG) semiconductors are known to have the potential to make a transformative impact on 21st century energy economy. However, their market penetration has been slow primarily due to high cost and unknown application-level reliability. This article presents a comprehensive report on the history, current state of the art, and impending challenges in WBG power semiconductor technologies in order to break open this gridlock.

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively.

According to a recent report by the International Energy Agency [1], although India is the second most populous country on earth, it ranks far behind other countries in terms of per capita electricity consumption and carbon footprint. As shown in Table 1, India is well below the world average in both per capita electricity consumption and carbon footprint indices. However, with an ambitious plan for rapid growth and economic development, India is poised to quickly increase its carbon footprint and become a major contributor to preventing global climate change.

Presents information on the IEEE International Conference on Sustainable Green Buildings and Communities Conference.

Much of the credit for 20th-century advances in computing and communication goes to the silicon transistor and the integrated circuit. The same may be said for the silicon insulated gate bipolar transistor (IGBT) with respect to the impending revolution taking place in energy technology. The silicon IGBT offers unprecedented energy efficiency when switching electrical power in the range of few hundred kilowatts to multimegawatts at a low manufacturing cost. It is transforming the electric utility, transportation, telecommunication, manufacturing, and medical infrastructures in a manner never seen before. This article pertains to the discovery and demonstration of early IGBT devices.

High-voltage (≥100 V) power diodes fabricated on wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride are generally rated for punch-through leakage current and employ a buffer layer sandwiched between the drift region and substrate. A simple and accurate method for the extraction of important diode design parameters is presented and validated using extensive static current-voltage and capacitance-voltage measurements of high-voltage (≥600 V) commercial SiC junction-barrier-controlled Schottky diodes from room temperature to 250 °C. It is shown that there is significant potential for further optimization of the performance of SiC power diodes.

The modular multilevel converter (MMC) is the most promising converter topology for medium- and high-power applications. One of the main concerns in the operation of the MMC, particularly for high-power applications, is its efficiency, which should be maximized. Silicon Carbide (SiC)-based devices have the potential to provide significant efficiency improvement compared with silicon devices. However, the possibility and impact of using SiC-based devices instead of silicon devices for high-power conversion have not been thoroughly explored. This paper reports on the results obtained from a detailed study to evaluate the performance of MMCs based on medium-voltage SiC MOSFETs and diodes with hybrid MMCs that employ silicon IGBTs and SiC diodes. The results are based on detailed circuit simulations that use simple physics-based circuit models. The study suggests the potential for significant efficiency gain for MMCs based on SiC power devices.

Simple and accurate circuit simulation models for high-voltage silicon carbide power MOSFETs and Schottky barrier diodes are presented and validated. The models are physics-based and consist of minimal number of model parameters that can be easily extracted from simple static $I$ – $V$ and $C$ – $V$ measurements. The models are used in a buck-boost bidirectional dc-dc converter, with and without an antiparallel Schottky diode. The efficiency of the converter was analyzed for synchronous and nonsynchronous operation of the switches. An optimal selection of the antiparallel Schottky diode is proposed to minimize the cost of the converter without compromising its efficiency.

To enable the rapidly emerging and imminent energy economy, high-voltage (HV) and high-current robust power electronic modules (PEMs) are needed at low cost. PEMs typically consist of a number of semiconductor power switches and driver chips; intelligent power modules often contain sensing and protection circuitry. In the entire supply chain of power electronics systems-from materials to end-user applications, including the original equipment manufacturers (OEMs)-the PEM is the key building block, as it forms the heart of a power electronic system. The performance, cost, and durability of the entire power electronic system critically hinge on those of the PEM. In addition, major business opportunities in power electronics are often enabled by the advances in power semiconductor devices. One such opportunity currently available to the power electronics community has been created by the advances in wide-bandgap (WBG) power switching devices, which were first introduced by Shenai et al. in the 1980s [1].

Current status of wide bandgap (WBG) semiconductor material technology is evaluated for developing high-performance and reliable power electronics switching converters. The study takes into account field reliability of silicon power metal-oxide-semiconductor field-effect transistors (MOSFETs) in compact computer/telecom power supplies where residual material defects present in the silicon space-charge region were found to generate local microplasma that eventually caused power MOSFETs to fail under long-term repetitive field-switching conditions. It is shown that silicon power MOSFETs with increased low-level leakage currents are more prone to field failures in high-density power supplies. A new single-event burnout (SEB) stress testing methodology is proposed; the SEB stress test results are shown to correlate well with silicon power MOSFET failures in power supply circuits. Based on these results and the current state of the art of silicon carbide (SiC) and gallium nitride (GaN) power devices, a “reliability-driven” manufacturing approach is recommended for rapid commercialization and market penetration of WBG semiconductor power devices.

Simple and accurate circuit simulation model for gallium nitride (GaN) power field-effect transistors (FETs) is presented and validated in high-frequency low-voltage synchronous buck (SB) dc-dc power converters. For comparison, simulation results are also presented for the power converter based on silicon power metal-oxide semiconductor (MOS)FETs with similar voltage and current ratings. An improvement in power conversion efficiency of more than 4% is reported with GaN power FETs compared to the best commercially available silicon power MOSFETs in a 19 V/1.2 V, 7 W SB dc-dc power converter with excellent load regulation. A temperature- and frequency-dependent power inductor model is also reported and is shown to be necessary in order to accurately model the converter performance.

Wide bandgap (WBG) semiconductors, especially silicon carbide (SiC) and gallium nitride (GaN), promise transformational advances in electrical power systems, with increased power conversion efficiency for transportation and renewable energy utilization. Compared with the semiconductor silicon, SiC and GaN materials offer significantly higher electrical and thermal conductivities, increased avalanche breakdown field strength, and improved ruggedness under extreme environmental operating conditions. These basic material properties translate into more compact and lightweight power conversion systems with significant energy savings, much improved signal sensing and transmission characteristics, and longer operating life in the field.

This paper studies the problem of providing recovery from link failures in optical wavelength division multiplexing (WDM) networks. One of the widely studied mechanisms is dynamic link restoration, which provides recovery by determining restoration paths around a link after a failure occurs. This mechanism leads to a lower backup resource utilization, fast failure signaling rate, and a scalable operation. However, one of the main drawbacks of uncoordinated dynamic restoration is the inability to provide a 100% recovery for all connections, especially at high network loads. An alternate solution is proactive protection, where backup capacity is reserved during connection setup that can guarantee recovery under certain conditions (e.g., single link failures) but requires higher backup capacity and has low spare capacity utilization when failures do not occur. This paper presents two hybrid survivability approaches that combine the positive effects of restoration and protection. The proposed algorithms make use of available or collected network state information, such as link load, to identify critical links or segments in the network that are then proactively protected. The overall goal of the proposed approaches is to improve the restoration efficiency by providing a tradeoff between proactive protection and dynamic restoration. This paper presents a detailed performance analysis of the proposed algorithms. Experimental results show that under high loads, both the proposed approaches maintain a consistent restoration efficiency of at least 10%, or higher, when compared to the basic restoration scheme.

This paper studies the connection-assignment problem for a time-division-multiplexed (TDM) wavelength-routed (WR) optical wavelength-division-multiplexing (WDM) network. In a conventional WR network, an entire wavelength is assigned to a given connection (or session). This can lead to lower channel utilization when individual sessions do not need the entire channel bandwidth. This paper considers a TDM-based approach to reduce this inefficiency, where multiple connections are multiplexed onto each wavelength channel. The resultant network is a TDM-based WR network (TWRN), where the wavelength bandwidth is partitioned into fixed-length time slots organized as a fixed-length frame. Provisioning a connection in such a network involves determining a time-slot assignment, in addition to the route and wavelength. This problem is defined as the routing, wavelength, and time-slot-assignment (RWTA) problem. In this paper, we present a family of RWTA algorithms and study the resulting blocking performance. For routing, we use the existing shortest path routing algorithm with a new link cost function called least resistance weight (LRW) function, which incorporates wavelength-utilization information. For wavelength assignment, we employ the existing least loaded (LL) wavelength selection; and for time-slot allocation, we present the LL time-slot (LLT) algorithm with different variations. Simulation-based analyses are used to compare the proposed TDM architecture to traditional WR networks, both with and without wavelength conversion. The objective is to compare the benefits of TDM and wavelength conversion, relative to WR networks, towards improving performance. The results show that the use of TDM provides substantial gains, especially for multifiber networks.

The Collider Detector at Fermilab (CDF) operates in the beamline of the Tevatron proton-antiproton collider at Batavia, IL. The Tevatron is expected to undergo luminosity upgrades (Run IIb) in the future, resulting in a higher number of interactions per beam crossing. To operate in this dense radiation environment, an upgrade of the CDF's silicon vertex detector subsystem and a corresponding upgrade of its VME-based DAQ system has been explored. Prototypes of all the Run IIb SVX DAQ components have been constructed, assembled into a test stand, and operated successfully using an adapted version of the CDF's network-capable DAQ software. In addition, a PCI-based DAQ system has been developed as a fast and inexpensive tool for silicon detector and DAQ component testing in the production phase. We present an overview of the Run IIb silicon DAQ upgrade, emphasizing the new features and improvements incorporated into the constituent VME boards and discuss a PCI-based DAQ system developed to facilitate production tests.

The main building block and readout unit of the planned CDF Run IIb silicon detector is a "stave," a highly integrated mechanical, thermal, and electrical structure. One of its characteristic features is a copper-on-Kapton flexible cable for power, high voltage, data transmission, and control signals that is placed directly below the silicon microstrip sensors. The dense packaging makes deadtime-less operation of the stave a challenge since coupling of bus cable activity into the silicon sensors must be suppressed efficiently. The stave design features relevant for deadtime-less operation are discussed. The electrical performance achieved with stave prototypes is presented.

This paper presents a study of the performance of high-voltage Si and 4H-SiC diodes in a DC-DC buck converter. Device operation in both hard- and zero-voltage switching conditions is presented with the help of measurements and two-dimensional (2-D) mixed device-circuit simulations. Experimental results show that SiC PiN diodes have a strong potential for use in high-speed high-voltage power electronics applications operating at high temperature. A combination of low excess carrier concentration and low carrier lifetime results in superior switching performance of the 4H-SiC diode over ultrafast Si diodes. Soft switching is shown to minimize the switching loss and allow operation at higher switching frequencies using Si diodes. The power loss of 4H-SiC diodes is dominated by conduction loss. Consequently, soft-switching techniques result in a marginal reduction in power loss. However, the low overall power loss implies that SiC diodes can be used at very high switching frequencies even in hard-switching configurations.

This paper presents the first results of a practical 30 V RF LDMOSFET in silicon-on-insulator (SOI) material. Its complete electrical characteristics, DC and radio frequency (RF), are presented. Bulk silicon LDMOSFETs are popular in RF power applications, and SOI promises to improve device characteristics, enhance integration and provide high-temperature robustness. This work demonstrates that SOI LDMOSFETs can deliver performance comparable to bulk Si using an SOI CMOS foundry with only minimal process enhancements. To investigate the impact of feature sizing in the LDD and gate length on the static and RF performance, 12 devices were fabricated. Characterization was done at the wafer level and devices were packaged and used to construct a class A RF amplifier. The devices exhibited a subthreshold slope of 214 mV/decade, a transconductance of 30 mS, and f/sub T/ up to 10.9 GHz. The amplifier had a maximum power output of 115 mW, gain of 14 dB, and a drain efficiency of 27% at P/sub out,/ /sub max/.

An integrated power electronics curriculum has been implemented in the Department of Electrical and Computer Engineering at the University of Illinois, Chicago. This paper describes the development of a set of hands-on laboratory experiments to accompany classroom lectures. Content is based on switching converter topologies and commercial power semiconductor devices. Unlike most experiments, which focus on circuit- or control-level characteristics, our approach emphasizes the circuit-device-load interactions. The concept presented is innovative in that it creates a 3/spl times/3 matrix of experiment variation-devices, circuits-control, and machines-loads-with one set of hardware. The lab development is ongoing with future experiments to address three-phase converters and motor control applications. Experiment content is described, as well as the means by which the material has been integrated within the course sequence. Lab station construction and safety issues are also addressed. The experiments require hands-on measurement and circuit connection and complement the established course elements of theory and computer-based circuit modeling. Laboratory experiments and computer simulations collectively provide quantitative evidence of mixed circuit and device optimization.

The collider detector at Fermilab is approaching the completion of the silicon vertex detector upgrade for Run II. The port card is a Beryllia multichip module developed to control, read out, and regulate power for the silicon strip readout chips. It has two radiation hard application-specific integrated circuits, parallel fiber-optic transmitters, and voltage regulators. It resides 14 cm from the accelerator beam inside the tracking volume. The function and location of the port card impose severe constraints on its design. This paper presents the port card and describes the adopted solutions to address the main design issues, as well as the result of many characterization tests.

This paper presents an innovative power electronics curriculum spanning the undergraduate and graduate programs. The curriculum develops the basic concepts of the field and applies them to modern industrial challenges to solve practical problems. It is based on three fundamental disciplines: switching devices, circuits and topologies and control and drives. The curriculum, which will facilitate the development of optimal systems, bridges the gap between power semiconductor devices and circuit design. An underlying principle of the curriculum is the development of optimal application-specific power electronics systems, achieved primarily through optimization of power semiconductor devices. The curriculum is described in detail with an emphasis on the courses pertaining to power semiconductor device physics and converter circuit design. The role of advanced computer-aided design tools is also identified and shown to facilitate an application-specific device design and optimization methodology. To further illustrate the effectiveness of this approach, two industry-relevant course projects performed in the curriculum are presented in detail.

This paper describes an improved lumped circuit model of power bipolar junction transistors (BJTs) that can predict the turn-off fall time to a greater accuracy than currently available models. Though the existing models simulate the storage time and delay time to a good accuracy, the fall time performance is neglected. This is because the existing models do not account for the charge decay due to recombination. The model presented in this paper is based on the charge dynamics of the device. The charge dynamics are explained in detail using simulation results from an advanced two-dimensional (2-D) device and circuit simulator. Based on a physical understanding of the charge dynamics, this model is implemented to incorporate the charge decay due to recombination to account for the current tail during turn-off. The lumped-circuit model is implemented in PSPICE using the existing quasisaturation model along with controlled sources. To validate the model, the device was subjected to hard- as well as soft-switching renditions (zero current switching and zero voltage switching). The modeled results are observed to have a good match with measured results.

The author describes how, when circuit and device designers jointly tailor power electronics systems to a specific application, performance and reliability can benefit at little or no cost.

Soft switching involves turning the semiconductor device on or off with minimal switching stress. Zero voltage switching (ZVS) and zero current switching (ZCS) are the two most popular variants of soft switching schemes. The turn-off performance of insulated gate bipolar transistors (IGBT's) under ZVS and ZCS environments is critically evaluated in this paper. It is shown that the turn-off mechanism under ZVS and ZCS conditions is dissimilar. Charge removal from the drift region during ZVS turn-off is mainly due to carrier sweep-out and recombination. On the other hand, charge removal through the channel during the phase of no device current is shown to be an important mechanism governing the magnitude and extent of the current tail during ZCS turn-off. This also results in significantly reduced turn-off losses of IGBT in ZCS as compared to ZVS. Improved understanding of internal carrier dynamics will lead to better utilization of IGBT in a soft-switching environment.

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices.

This paper presents an analytical study of the RF performance of Si power MOSFET's. Si MOSFET's are rapidly becoming popular in RF applications. Although circuit simulation models have been presented explaining the static performance of these devices, the correlation of device physical parameters with RF performance has not been studied extensively. In this paper, based on the equivalent circuit representation of a power MOSFET, static and large-signal analysis have been carried out to study the RF performance for VDMOSFET and LDMOSFET devices. It has been shown that transconductance compression due to the JFET region leads to degradation of high-power RF performance. It is also shown that LDMOSFET has higher power gain than VDMOS, but steeper degradation with input power. Velocity saturation in the MOS channel and presence of the JFET region are shown to strongly influence the RF performance of the two devices.

The application of insulated gate bipolar transistors (IGBTs) in high-power converters subjects them to high-transient electrical stress such as short-circuit switching and turn-off under clamped inductive load (CIL). Robustness of IGBTs under high-stress conditions is an important requirement. Due to package limitations and thermal parameters of the semiconductor, significant self-heating occurs under conditions of high-power dissipation, eventually leading to thermal breakdown of the device. The presence of a parasitic thyristor also affects the robustness of the device. In order to develop optimized IGBTs that can withstand high-circuit stress, it is important to first understand the mechanism of device failure under various stress conditions. In this paper, failure mechanisms during short-circuit and clamped inductive switching stress are investigated for latchup-free as well as latchup-prone punchthrough IGBTs. It is shown that short-circuit and clamped inductive switching cannot be considered equivalent in the evaluation of a device safe operating area (SOA). The location of thermal failure of latchup-free punchthrough IGBTs is shown to be different for the two switching stresses.

As circuit switching frequency continues to increase, there is a need to produce faster rectifiers with lower power losses. Efficient utilization of high-power ultrafast rectifiers requires precise knowledge of the key static and dynamic switching parameters, especially the reverse-recovery characteristics. Conventional reverse-recovery test circuits were developed to test rectifiers with reverse-recovery times (t/sub RR/) greater than 100 ns, however, new measurement techniques are needed for accurate characterization and modeling of the high-power ultrafast rectifier reverse-recovery process. A test circuit topology is proposed which offers several advantages over existing test circuits. This circuit offers the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/dt. This circuit is also studied using a two-dimensional (2-D) mixed device and circuit simulator in which the device under test is represented as a 2-D finite-element grid and the semiconductor equations are solved under boundary conditions imposed by the proposed test circuit. This simulation tool is used to understand the device physics of the reverse-recovery process and develop more accurate models to be implemented in behavioral circuit simulators. The simulation results are then compared to the measured data for a silicon P-i-N and 200-V GaAs Schottky rectifier under various measurement conditions. Simulation results are shown to be in excellent agreement with the measured data.

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies.

This paper reports the internal dynamics of insulated gate bipolar transistors (IGBT's) under short-circuit switching conditions. Short-circuit performance of IGBT's has been studied in detail with the aid of extensive measurements and numerical simulations. An advanced two-dimensional (2-D) mixed device and circuit simulator that incorporates the self-heating mechanism has been employed to examine IGBT behavior under short-circuit stress. Latch-up free punchthrough IGBT has been examined. It is shown that hot-spot generation due to current crowding and impact ionization is the cause of breakdown of an IGBT under short-circuit switching.

Consumer demand for portable computing and mobile wireless communications will continue to drive development of functionally integrated, ultra-low-power systems on a chip. CMOS bulk processing is likely to emerge as the foundation of mixed-signal, ultra-low-power ICs because of its inherent advantages for low-power logic and flexibility in RF applications. To successfully meet time-to-market goals and shrink product-development cycles, computer-aided design tools must guide a design from conceptualization to physical implementation. Estimates of floorplan arrangement and interconnect and package parasitics are necessary early in the design flow, since these undesirable contributions can dominate over the intrinsic device parasitics.

The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs.

The switching performance of silicon (Si) punchthrough (PT) and a nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is compared under zero voltage switching (ZVS), both experimentally and using two-dimensional (2-D) device simulator. Extensive experimental results are obtained for both the devices under ZVS turn-on and turn-off, under a wide range of operating conditions. The switching performance is then analyzed using a finite element based device simulator which shows good agreement with the measured data. The device simulator is used to study the turn-on and turn-off behavior of the two devices. It is shown that, although both the devices behave similarly during ZVS turn-on, with the characteristic forward recovery voltage spike due to "conductivity modulation lag," the turn-off wave forms during ZVS are different for the two devices. Punchthrough device shows a "tail bump" during turn-off as opposed to a "tail plateau" shown by nonpunch-though device. The device simulator is used to study this difference in turn-off behavior. The simulator is also used to analyze the characteristic ZVS turn-on voltage wave form in more detail. Temperature dependence of the static and ZVS characteristics is also studied, for both the devices, and it is pointed out that turnoff of an NPT-IGBT is much less dependent on temperature as opposed to that of a PT-IGBT.

Clamped inductive switching performance of insulated gate bipolar transistors (IGBTs) have been studied in detail with the aid of extensive measurements and numerical simulations. Internal dynamics of a latch-up free punch-through IGBT during clamped inductive switching is studied using two-dimensional (2-D) mixed device and circuit simulations incorporating the self-heating mechanism. Failure of IGBT during inductive load turn-off is shown to occur due to thermally assisted carrier multiplication at the reverse biased p-base n-drift region junction under the emitter contact.

The ruggedness of scaled power DMOSFET's under unclamped inductive switching (UIS) conditions is studied using an advanced two-dimensional (2-D) device simulator. It is shown that at the onset of device turnoff, significant self-heating occurs within the intrinsic device which leads to an increase in the avalanche breakdown voltage of the device. The self-heating mechanism is incorporated by self-consistently solving heat generation and diffusion equations with semiconductor charge balance and transport equations. The power module is modeled by accounting for various thermal resistances including those contributed by the package, contact metallization and intrinsic device material. The simulation results are compared with extensive UIS measurements and it is shown that the simulations can be used to identify local "hot spots" and the design and process parameters that lead to thermal runaway.

The turn-off of IGBTs in hard- and soft-switching converters is analyzed using nonquasi-static analysis. It is shown that while the turn-off current waveform for hard-switching is governed solely by the device for a particular value of on-state current and bus voltage, turn-off current waveform for soft-switching is strongly dependent on device-circuit interactions, so that a trade-off between turn-off loss and switching time can be made using external circuit elements. Models are developed to explain IGBT turn-off for both hard- and soft-switching conditions. Hard-switching considers both inductive and resistive loads. Calculated results are validated by comparison with results of measurements and two-dimensional (2-D) numerical simulations.

This paper presents a novel P-i-N diode which is suitable to be used as an anti-parallel diode in an IGBT module. It is shown that the switching performance of the module is significantly improved with the new diode structure, under hard-switching conditions. Diode performance in commercially available IGBT modules is studied under hard-switching conditions, both experimentally and using a finite element based device simulator. The device simulator is then used to study and compare the performance of the new diode structure with commercially available devices. It is shown that the new structure gives superior switching performance at the cost of a small increase in its on-state voltage drop. It is also shown that the switching characteristics of the new diode show a dramatic improvement over the conventional P-i-N diode at high temperatures.

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p/sup +/ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions.

The reverse recovery characteristics of high-power GaAs Schottky rectifiers are reported at various temperatures; mixed device and circuit simulations were used to study the internal plasma dynamics during the reverse recovery process. In this approach, semiconductor transport and heat generation and diffusion equations were solved self-consistently using a two-dimensional (2-D) finite element grid structure under boundary conditions imposed by the measurement circuit. The simulation results are shown to be in good agreement with the measured data at temperatures in the range of 25/spl deg/C to 125/spl deg/C. These results are compared with the reverse recovery characteristics of a commercial silicon PIN power rectifier under identical conditions and it is shown that carrier depletion is the dominant mechanism causing the reverse recovery in a GaAs Schottky diode. The reverse recovery power loss is negligible in a GaAs Schottky rectifier and is shown to decrease as the case temperature is increased, contrary to the silicon PIN rectifier behaviour.

The switching dynamics of insulated gate bipolar transistors (IGBT's) in zero voltage switching (ZVS) resonant converter applications is studied and optimized using an advanced mixed device and circuit simulator. It is shown that bipolar and MOS device parameters must be carefully optimized to obtain the lowest total power loss. A simple circuit simulation model was used in an advanced behavioral circuit simulator where the model parameters were extracted from mixed device and circuit simulations. Performance analysis of a typical series resonant converter (SRC) shows that ZVS condition is more favorable than the zero current switching (ZCS) condition from the standpoint of obtaining efficient power conversion. It is shown that IGBT's with narrower source result in lower total switching power loss.

The performances of the Insulated Gate Bipopar Transistor (IGBT) and MOS-Controlled Thyristor (MCT) in hard- and soft-switching applications are studied in detail, both experimentally and by using numerical simulations. Simulated results show good qualitative agreement with the measured data under a wide range of circuit operating conditions. The simulation results are obtained from an advanced mixed device and circuit simulator in which the device under test (DUT) is represented by a two-dimensional (2-D) grid structure and the internal plasma dynamics is studied using a finite element numerical solution technique. A comparison is then made between the switching performance of the bipolar transistor-like device (IGBT) and a thyristor-like device (MCT) in power converters. It is shown that due to a basic difference in the turn-off mechanism, whereas an IGBT shows a tail-current "bump" due to electric field buildup during turn-off, the MCT shows a turn-off "shoulder" due to current flow through the turn-off MOS channel. This leads to much higher losses for MCT than IGBT under identical operating conditions. Furthermore, since the turn-off of MCT involves removal of more carriers from the drift-region, the turn-off is slower than IGBT.