70 results on '"Sinanoglu, Ozgur"'
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2. VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques
3. $\tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems
4. SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks
5. Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks
6. Progressive Learning With Recurrent Neural Network for Sequence Classification
7. Leveraging Ferroelectric Stochasticity and In-Memory Computing for DNN IP Obfuscation
8. GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation
9. A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating
10. GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
11. Digitally Assisted Mixed-Signal Circuit Security
12. AntiDOTE: Protecting Debug Against Outsourced Test Entities
13. PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans
14. GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking
15. Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems
16. OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking
17. Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing
18. FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator
19. Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques
20. RESCUE: Resilient, Scalable, High-corruption, Compact-Key-Set Locking Framework
21. Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices
22. Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques
23. Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation
24. ScanSAT: Unlocking Static and Dynamic Scan Obfuscation
25. A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects
26. Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking
27. SuperVAULT: Superparamagnetic Volatile AUxiLiary Tamper-Proof Storage
28. Guest Editorial: Special Issue On Emerging Technologies in Computer Design
29. UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking
30. Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
31. Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC
32. Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
33. 2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets
34. Power Side-Channel Attacks in Negative Capacitance Transistor
35. Keynote: A Disquisition on Logic Locking
36. Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime
37. Removal Attacks on Logic Locking and Camouflaging Techniques
38. Logic Locking With Provable Security Against Power Analysis Attacks
39. Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits
40. SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory
41. Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) – Unlocked
42. Toward Physically Unclonable Functions From Plasmonics-Enhanced Silicon Disc Resonators
43. Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications
44. Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design
45. Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging
46. Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases
47. Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers
48. Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities
49. Adaptive Reduction of the Frequency Search Space for Multi- $V_{\mathrm{ dd}}$ Digital Circuits Using Variation Sensitive Ring Oscillators
50. A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications
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