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All DC offshore wind farms are gaining popularity for long-distance and high-power offshore wind energy conversion. It calls for high-power DC/DC converter with high step-up ratio for interconnecting the medium-voltage DC collection and the high-voltage DC transmission systems. This paper proposes a monopolar symmetrical DC/DC converter, which is featured with partial-power processing and presents less installed capacity of components, low cost, low power loss, lightweight, and small footprint. Moreover, a modified phase-shifted carrier pulse-width modulation with variable carrier frequency is developed to further reduce the switching loss and keep the dynamic current tracking performance. Effectiveness of the proposed converter has been verified by simulation study of a 400MW, 25kV/250kV model and experimental results of a 5.4kW, 60V/320V scaled-down prototype.

A temperature sensor named a thermillator (thermo-oscillator) is demonstrated, consisting of a single device with an n+-emitter, p-base and n+-collector. The thermillator with a p-base floating body shows inherent oscillation behavior. The underlying mechanism of the thermillator is based on the single transistor latch (STL). Oscillation originates with the iterative charging and discharging process in the floating p-base, and the oscillation frequency ( $\boldsymbol {f}$ ) is sensitively changed by applied temperature. Compared to a temperature sensor with a circuit-based ring oscillator, the single device-based thermillator has the advantages of small footprint area, low hardware cost, and low power consumption.

Three-dimensional large scale integration (3D-LSI) packaging is crucial toward obtaining increased circuit density within a small footprint. In a 3D-LSI package, chip-to-chip interconnection is typically obtained using through-silicon vias and microbumps. In particular, microbumps realized by nanoparticle deposition (NPD) are promising to obtain high-density interconnections. However, the effect of temperature on the mechanical properties (i.e., hardness) of NPD bumps is little understood. This paper seeks to investigate the influence of temperature on the hardness of NPD bumps, with reference to NPD films. The results obtained suggest a significant reduction in the NPD bump hardness from room temperature to 200 °C. In particular, the hardness was observed to be mainly dependent on temperature rather than grain size, as the grain microstructures obtained at room temperature and 200 °C are similar. Overall, these results suggest a simple approach to control the NPD bump compression during flip-chip bonding, where the hardness-temperature data for the NPD bumps suffices to estimate for the bump compression during flip-chip bonding.

Long short-term memory RNNs (LSTMRNNs) have shown great success in the Automatic speech recognition (ASR) field and have become the state-ofthe- art acoustic model for time-sequence modeling tasks. However, it is still difficult to train deep LSTM-RNNs while keeping the parameter number small. We use the highway connections between memory cells in adjacent layers to train a small-footprint highway LSTM-RNNs (HLSTM-RNNs), which are deeper and thinner compared to conventional LSTM-RNNs. The experiments on the Switchboard (SWBD) indicate that we can train thinner and deeper HLSTM-RNNs with a smaller parameter number than the conventional 3-layer LSTM-RNNs and a lower Word error rate (WER) than the conventional one. Compared with the counterparts of small-footprint LSTMRNNs, the small-footprint HLSTM-RNNs show greater reduction in WER.

In this letter, the performance of a diffractive gradient index lens antenna, constructed by using dielectric subwavelength structuration and manufactured by three-dimensional printing, is compared to the ones of conventional lens antennas in a small footprint configuration. It discusses the advantages and drawbacks of each configuration and compares the simulated and measured gain performances. It shows that structured lens antenna can achieve gain superior to conventional approaches, combined with a 1 dB bandwidth of 10.9%, thanks to the engineering of artificial gradient index. All these benefits are coming with a significant decrease in the antenna weight for the same footprint.

With increasing data demand, wireless networks are evolving to a hierarchical architecture where coverage is provided by both wide-area base-stations (BS) and dense deployments of short-range access nodes (AN) (e.g., small cells). The dense scale and mobility of users provide new challenges for scheduling: (i) High flux in mobile-to-AN associations, where mobile nodes quickly change associations with access nodes (time-scale of seconds) due to their small footprint, and (ii) multi-point connectivity, where mobile nodes are simultaneously connected to several access nodes at any time. We study such a densified scenario with multi-channel wireless links (e.g., multi-channel OFDM) between nodes (BS/AN/mobile). We first show that traditional algorithms that forward each packet at most once, either to a single access node or a mobile user, do not have good delay performance. We argue that the fast association dynamics between access nodes and mobile users necessitate a multi-point relaying strategy, where multiple access nodes have duplicate copies of the data, and coordinate to deliver data to the mobile user. Surprisingly, despite data replication and no coordination between ANs, we show that our algorithm (a distributed scheduler — DIST) can approximately stabilize the system in large-scale instantiations of this setting, and further, performs well from a queue-length/delay perspective (shown via large deviation bounds).

A low profile dual-circularly polarized printed ring-slot antenna with a small footprint, which radiates above an open cavity loaded with an artificial magnetic conducting reflector, is presented. The feed network consists of two T-shaped capacitive feed structures connected to a miniaturized hybrid branch-line coupler. Experimental results for a final antenna design (with a size of $0.5\lambda _{\mathrm {\mathbf {0}}} \quad \times 0.5\lambda _{\mathrm {\mathbf {0}}} \quad \times 0.057\lambda _{\mathrm {\mathbf {0}}}$ ) show a 4% isolation bandwidth between the two ports of the dual-circularly polarized antenna and a maximum gain of approximately 6.8 dBic. Good front-to-back ratios and low cross-polarization were achieved. These very compact and low profile antennas are suitable for 2.4 GHz wireless local area network (WLAN) communication systems.

A hybrid plasmonic modulator based on microdisk resonators enhanced with electro-optic polymers is presented. Modulation is achieved by dynamically controlling an electromagnetically induced transparency window using a push–pull driving configuration. The proposed device combines small footprint, high modulation depths, low insertion losses, and low power consumption. By properly selecting the voltage values and the microdisk radii, modulation at different wavelengths and tunable spectral filtering are achieved.

3-D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3-D ICs. Recent work on the optimization of 3-D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter space. In realistic scenarios, the assumed values for parameters such as test power and pattern count of logic cores, which are used for optimizing the test architecture for a die, may differ from the actual values that are known only after the design stage. In a 3-D setting, a die can be used in multiple stacks with different properties. As a result, the originally designed test architecture is no longer optimal, which leads to an undesirable increase in the test cost. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations. We formulate a mathematical model for the robust test-architecture optimization problem, and propose an efficient heuristic to solve the problem even for large designs in reasonable time. The proposed optimization framework is evaluated using the ITC’02 SoC benchmarks and we show that robust solutions are superior to single-point solutions in terms of average test time when there are uncertainties in the values of input parameters.

A concatenative text-to-speech (CTTS) synthesizer requires a large acoustic database for high-quality speech synthesis. This database consists of many acoustic leaves, each containing a number of short, compressed, speech segments. In this paper, we propose two algorithms for recompression of the acoustic database, by recompressing the data in each acoustic leaf, without compromising the perceptual quality of the obtained synthesized speech. This is achieved by exploiting the redundancy between speech frames and speech segments in the acoustic leaf. The first approach is based on a vector polynomial temporal decomposition. The second is based on 3-D shape-adaptive discrete cosine transform (DCT), followed by optimized quantization. In addition we propose a segment ordering algorithm in an attempt to improve overall performance. The developed algorithms are generic and may be applied to a variety of compression challenges. When applied to compressed spectral amplitude parameters of a specific IBM small footprint CTTS database, we obtain a recompression factor of 2 without any perceived degradation in the quality of the synthesized speech.

A microelectromechanical systems (MEMS) rotary microgripper incorporating electrothermal force sensors is reported. The device is fabricated using a standard SOI-MEMS process and achieves a stroke of (90 \(\mu \) m) at a relatively low voltage (

Metal wires for global communication on integrated circuits have become problematic as device integration densities scale with rapid advancements in CMOS technology. They may not be able to deliver the growing bandwidth requirements of future microprocessors. Optical interconnect technologies may provide a solution to meet this challenge and extend Moore's law. In this paper, a novel guided-wave optical interconnect fabric aiming to replace the slow global metal interconnections is proposed and analyzed. The reflection-mode multiple-quantum-well-modulator-based optical interconnection approach is projected to achieve high coupling efficiency and be compatible with standard CMOS processes. The key notion is a prismatic coupling structure that is embedded in the optical waveguide and therefore has a very small footprint in the circuit. Ray-trace and finite-difference time-domain simulation results predict high coupling efficiency of this structure.

Although novel architectures such as cell processors, graphics processors, and FPGAs are growing in popularity, conventional microprocessor designs pack a punch in a small footprint and are widely supported by commodity operating system and development tools. In this installment of Scientific Programming, we're going to talk about our initial foray into embedded Linux running on the slug, which is the pet name for the Linksys NSLU2, a home "appliance" aimed at providing network-attached storage.

Silicon photonics could enable a chip-scale platform for monolithic integration of optics and microelectronics for applications of optical interconnects in which high data streams are required in a small footprint. This paper discusses mechanisms in silicon photonics for waveguiding, modulating, light amplification, and emission. These mechanisms, together with recent advances of fabrication techniques, have enabled the demonstration of ultracompact passive and active silicon photonic components with very low loss.

The ultrasmall arrowhead arrayed-waveguide grating (AWG) with integrated waveguide mirrors has been proposed. The v-shaped bend waveguides, using integrated waveguide elliptic mirrors, were applied to the arrayed waveguide to reduce the AWG size. The small footprint leads to a low-cost waveguide device and decreases the phase error resulting from refractive index fluctuations. The eight-channel 40-GHz-spacing arrowhead AWG was fabricated from silica, with a refractive index difference of 0.75%. The size of this arrowhead AWG was 1.3 /spl times/ 11.6 mm, being 1/10 of the size of the conventional one. The insertion loss and the adjacent crosstalk were 8.31 and -28.3 dB, respectively.

Three design methods, widely used for high frequency inductors and transformers, are critically compared using, as a basis, the example of low profile, small footprint, low loss 500 kHz devices. In comparison to the results obtained from more detailed finite element models, it is shown that the standard methods provide surprisingly good estimates of the copper and core losses.

A technique for the handset antenna field combining a PIFA and a slot in presented. The antenna concept features a small footprint and multi-band operation which is required for the new generation of thin profile handset phones.

A graded base SiGe HBT optical modulator has high-speed, high optical modulation efficiency, small footprint. In this paper, we present our work in the design and modeling of an HBT optical modulator, its driver circuit and fabrication and integration. A high-efficient HBT electro-optical (EO) modulator with π phase-shift length of 22.6 μm is investigated. The speed of this modulator is calculated to be 30 Gb/s. To verify the functionality of HBT structure as an EO modulator, an 80 Gb/s serializer and driver with an HBT modulator is fabricated by the IBM 8HP BiCMOS process, which has much higher speed but lower modulation efficiency.