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BackgroundNeurons demonstrate very distinct nonlinear activation dynamics, influenced by the neuron type, morphology, ion channel expression, and various other factors. The measurement of the activation dynamics can identify the neural target of stimulation and detect deviations, e.g., for diagnosis. This paper describes a tool for closed-loop sequential parameter estimation (SPE) of the activation dynamics through transcranial magnetic stimulation (TMS). The proposed SPE method operates in real time, selects ideal stimulus parameters, detects and processes the response, and concurrently estimates the input–output (IO) curve and the first-order approximation of the activated neural target.ObjectiveTo develop a method for concurrent SPE of the first-order activation dynamics and IO curve with closed-loop TMS.MethodFirst, identifiability of an integrated model of the first-order neural activation dynamics and IO curve is assessed, demonstrating that at least two IO curves need to be acquired with different pulse widths. Then, a two-stage SPE method is proposed. It estimates the IO curve by using Fisher information matrix (FIM) optimization in the first stage and subsequently estimates the membrane time constant as well as the coupling gain in the second stage. The procedure continues in a sequential manner until a stopping rule is satisfied.ResultsThe results of 73 simulation cases confirm the satisfactory estimation of the membrane time constant and coupling gain with average absolute relative errors (AREs) of 6.2% and 5.3%, respectively, with an average of 344 pulses (172 pulses for each IO curve or pulse width). The method estimates the IO curves’ lower and upper plateaus, mid-point, and slope with average AREs of 0.2%, 0.7%, 0.9%, and 14.5%, respectively. The conventional time constant estimation method based on the strength-duration (S–D) curve leads to 33.3% ARE, which is 27.0% larger than 6.2% ARE obtained through the proposed real-time FIM-based SPE method in this paper.ConclusionsSPE of the activation dynamics requires acquiring at least two IO curves with different pulse widths, which needs a controllable TMS (cTMS) device with adjustable pulse duration.SignificanceThe proposed SPE method enhances the cTMS functionality, which can contribute novel insights in research and clinical studies.

Modular multilevel converters (MMCs) feature an established topology for the highest voltage and power levels. For lower levels, MMCs find a wide range of applications in generation, energy storage, and electric motor drive. However, the large quantity of expensive voltage sensors as well as high data-processing requirements for the module voltage balancing remains an obstacle. Additionally, the stark cost reductions of power electronic semiconductors have reduced their share in the total cost and rendered initially uneconomical module topologies appealing in low and medium voltages. In this article, we proposed an MMC topology with an active clamping path that balances the voltage of the modules in an arm. The proposed structure can achieve sensorless voltage balancing with a minimum control effort. The sensorless operation has the added benefit of reducing the communication as well as computation demand between the modules and the central controller. As compared with the state-of-the-art voltage balancing schemes, the proposed solution achieves a balanced system operation with less power loss, fewer components, and without any measurement. The presented analysis as well as the simulation and experimental results verify the benefits of the proposed topology. The results demonstrate that even in the face of a severe imbalance, all the module voltages are maintained within tight boundaries.

Modular multilevel converters (MMCs) enjoy the benefits of modularity and scalability. In particular, MMCs with symmetrical half-bridge submodules enable bipolar operation yet with a simple structure and low conduction losses. However, bulky dc capacitors in MMC submodules act as one major obstacle that retards the further improvement of system size, weight, and cost performance. Additionally, tight regulation and balance of dc capacitor voltages necessitate expensive voltage sensors paired with dedicated voltage controllers. This article proposes an effective hardware-based strategy that achieves MMC capacitance reduction through parallelization of symmetrical half-bridge submodules. On top of capacitance saving, the proposed strategy balances capacitor voltages in a sensorless fashion, which translates into the removal of voltage sensors and great simplification of control efforts. In addition, the proposed strategy allows fault-tolerant operation of MMCs. Finally, simulation and experimental results validate the effectiveness of the proposed strategy in capacitance reduction and capacitor voltage balancing of MMCs as static compensators.

Objective: This work aims to reduce the acoustic noise level of transcranial magnetic stimulation (TMS) coils. TMS requires high currents (several thousand amperes) to be pulsed through the coil, which generates a loud acoustic impulse whose peak sound pressure level (SPL) can exceed 130 dB(Z). This sound poses a risk to hearing and elicits unwanted neural activation of auditory brain circuits. Methods: We propose a new double-containment coil with enhanced winding mounting (DCC), which utilizes acoustic impedance mismatch to contain and dissipate the impulsive sound within an air-tight outer casing. The coil winding is potted in a rigid block, which is mounted to the outer casing by its acoustic nodes that are subject to minimum vibration during the pulse. The rest of the winding block is isolated from the casing by an air gap, and sound is absorbed by foam within the casing. The casing thickness under the winding center is minimized to maximize the coil electric field output. Results: Compared to commercial figure-of-eight TMS coils, the DCC prototype has 10-33 dB(Z) lower SPL at matched stimulation strength, whilst providing 22% higher maximum stimulation strength than equally focal commercial coils. Conclusion: The DCC design greatly reduces the acoustic noise of TMS while increasing the achievable stimulation strength. Significance: The acoustic noise reduction from our coil design is comparable to that provided by typical hearing protection devices. This coil design approach can enhance hearing safety and reduce auditory co-activations in the brain and other detrimental effects of TMS sound., 8 pages, 5 figures

Cascaded H-bridge and modular multilevel converters (MMC) are on the rise with emerging applications in renewable energy generation, energy storage, and electric motor drives. However, their well-known advantages come at the price of complicated balancing, high-bandwidth isolated monitoring, and numerous sensors that can prevent MMCs from expanding into highly cost-driven markets. Therefore, an obvious trend in research is developing control and topologies that depend less on measurements and benefit from simpler control. Diode-clamped topologies are considered among the more applicable solutions. The main problem with a diode-clamped topology is that it can only balance the module voltages of a string in one direction; therefore, it cannot provide a completely balanced operation. This article proposes an effective balancing technique for the diode-clamped topology. The proposed solution exploits the dc component of the arm current by introducing a symmetrically level-adjusted phase-shifted modulation scheme, and ensures the balancing current flow is always in the correct direction. The advantages of this method are sensorless operation, reduced computation, and control effort, lower communication requirement, removing the voltage sensors, and low overall cost. Analysis and detailed simulations provide insight into the operation of the new balancing technique and the experimental results confirm the provided discussions.

High-power silicon field-effect transistors as well as insulated gate bipolar transistors and particularly wide-bandgap semiconductor transistors typically need negative turn- off voltage for a secure off -state, resilience to spurious turn on , and rapid transition through the saturation mode. We present a gate driver configuration with compact and very efficient supply of the high and low sides of power transistor bridges with asymmetric bipolar control voltages without the need for costly and lossy isolated dc–dc converter and only low-voltage active components. The underlying negative voltage gate driver supply circuit consists of only a few cost-efficient components, its electrical potential is referenced to the source of the controlled semiconductor power switch, and its operation is synchronized with the gate driver output. It outcompetes the established use of isolated dc–dc converters in gate circuits with negative voltage needs with respect to cost, size, reliability, and efficiency. Importantly, the proposed negative voltage supply allows bootstrapping without the need for controllable high-voltage semiconductors for the sake of further cost reduction. We present detailed design rules of the circuit and experimentally validate circuit and control. In the automotive prototype implementation, size of the gate driver supply was reduced by 61%, cost by 57%, and loss by more than 16%.

Electrification has been a key component of technological progress and economic development since the industrial revolution. It has improved living conditions, spurred innovation, and increased efficiency across all sectors of our economy and all aspects of our lives. During the coming decades, electrification is expected to reach further and deeper into the transportation, building, and industry sectors, mainly motivated by the energy transition to a zero-carbonemission-based economy to mitigate climate change.

This article proposes a novel bipolar-type dc system suitable for both distribution and transmission systems based on modular multilevel series/parallel converters (MMSPCs). The system features decoupled operations of each pole of the bipolar system, being able to operate in both asymmetrical and regenerative modes. This enables two independent dc systems by using a single grid-tied converter. The MMSPC is based on a three-switch cell configuration and enables a simple balancing mechanism in combination with a wide range of output voltage frequencies. The simple balancing mechanism is the key to enable the dc operation and lead to simpler scalability for different voltage levels. Theoretical studies and experimental results are provided to verify and characterize the proposed system.

Since the introduction of modular multilevel converters (MMC), various additional features have been introduced for MMCs, among them parallel inter-module connectivity. However, such a parallel mode requires appropriate modulation and switching strategies to exploit its full potential. Low-frequency switching modulation is widely used with half-bridge modules and a large body of research focusses on the optimum control and scheduling of these methods. However, so far, a suitable adaptation for MMCs with parallel mode is missing, and existing methods perform suboptimum. This article proposes a generic scheduling algorithm for simple and low-cost integration with low-frequency switching modulation. The proposed method reduces control complexity, minimizes power loss, and can be combined with most modulation techniques, including nearest-level modulation (NLM) and selective harmonic elimination. The text in this article provides a general algorithm for integrating this method with other control levels and analyzes its effect on MMCs with parallel functionality. Moreover, it examines the performance of the system with NLM combined with the proposed scheduler and compares it to other alternatives. Results show up to a 50% reduction in power loss with a similar modulation technique as well as significantly lower THD and power loss compared to optimized phase-shifted carrier modulation as another sensorless alternative method.

This article proposes an optimal discontinuous pulsewidth modulation (ODPWM) strategy to reduce the zero-sequence circulating current (ZSCC) for paralleled three-phase two-level converters. While existing methods generally entail a tradeoff between the ZSCC peak and the switching losses, this article fully explores the redundancy in the vector sequences to further improve both objectives. First, we derive eight candidate vector sequences for 60° sectors, each sequence with minimal switching times and ZSCC changing rate. Second, we divide each 60° sector into 12 subsectors, each is equipped with one of the eight candidates. The comparisons show that the proposed method maintains the same maximum ZSCC peak of existing best methods while using the minimal switching times, or effectively reducing the switching loss by up to 50%; the ZSCC of the proposed method is minimal across the major modulation regions, guaranteeing a smaller loss of the common mode inductor and further reducing the semiconductor losses. We implement the proposed optimal vector sequences in a carrier-based modulation scheme, the references of which depends on the subsector. Despite the complex geometry of the subsectors, the decision procedure is simple. Finally, the experimental results confirm the effectiveness of the proposed ODPWM.

In more-electronics power systems, grid-forming power converters, which operate as ac voltage sources, regulate the grid frequency and voltages in replacement of synchronous generators. Notably, grid impedances greatly influence the small signal and voltage stability of grid-forming converters. As such, prior knowledge of grid impedances can be very helpful for controller design. However, grid impedance estimation schemes are normally designed for current-controlled grid-following converters. Moreover, they are either very complicated or only yield grid inductances in a generally intrusive way. To fill this research gap, an impedance estimation method well suited to grid-forming converters is proposed. The method consists of four operating modes, which work well in voltage and power control cases. In the voltage control case, the voltage amplitude perturbation or phase angle information is exploited. Subsequently, the grid inductance and resistance are derived from power measurement. Alternatively, the active or reactive power information serves to estimate the grid impedance in the power control case. The proposed method features an easy implementation without any harmonic distortion, safety concern, or dependence on control parameters. Moreover, the method operates nonintrusively in most scenarios. Furthermore, a novel Kalman filtering scheme is proposed to provide added incentives. Finally, simulation and experimental results validate the effectiveness and simplicity of the proposed method.

H-bridge-based multilevel converters (e.g., cascaded H-bridge converters) benefit from modularity and scalability. However, they suffer from the complexity and costs associated with a large count of semiconductor switches, together with their drivers and peripheral circuits, as well as higher conduction losses as compared to half-bridge-based counterparts, as two switches in each submodule must simultaneously conduct to provide a current path. To reduce the number of active switch semiconductors and conduction losses, this article proposes novel multilevel converters with symmetrical half-bridge submodules. The symmetrical half-bridge submodule features a bipolar voltage output, a reduced switch count, and simplicity. Furthermore, this article proposes a sensorless voltage balance scheme that successfully gets rid of capacitor voltage mismatch problems through diodes and submodule parallelization. This scheme can greatly reduce capacitor voltage ripples, thereby allowing the saving of dc capacitances, particularly in the case of numerous submodules. Finally, simulation and experimental results validate the superiority of the proposed multilevel converters and voltage balance scheme.

Cascaded multilevel converters have been gaining popularity in static compensators (STATCOMs) owing to their excellent modularity, output quality, and fault tolerance. However, cascaded multilevel converters require a large number of galvanically isolated voltage sensors and complex communication systems in order to balance the module dc-link voltages. This article proposes a reduced series/parallel module (RSPM) that intends to replace H-bridges in cascaded multilevel STATCOMs. Any adjacent RSPMs can be configured in series, bypass, or parallel. Cycling the parallel state through all modules balances all capacitor voltages in a sensorless manner. Since the RSPM-balancing process occurs at the hardware level, H-bridges can be easily replaced by RSPMs without changing higher-level control loops. Compared to existing series/parallel modules, the RSPM has the same functionalities but uses 25% fewer transistors. Despite the reduced switch count, the RSPM is shown to achieve even better efficiency under certain load conditions. The RSPM also attains similar semiconductor utilization ratio as H-bridge modules. The features of the RSPMs are verified on simulations and a down-scaled experimental setup.

This article aims to obtain the optimal combination of the switching loss, maximum zero-sequence circulating current (ZSCC), and line current ripple, which benefits most of the applications. The analysis shows that the interleaved discontinues pulsewidth modulation (IDPWM) maintains the minimum switching loss and line current ripples, but it introduces a larger ZSCC. Therefore, to obtain the optimal combination of the switching loss, maximum ZSCC peak, and line current ripple, it is essential to retain the minimum switching times and the optimal line current ripple of IDPWM but further reducing its overly large ZSCC. Further analysis reveals that IDPWM includes the vector combinations with medium ZSCC change rates, resulting in the larger ZSCC. Given the redundancies of the vector combinations, this article proposes a simple matrix to modify the original modulation signals of IDPWM, eliminating the medium ZSCC change rates. The proposed PWM scheme retains the minimum line current ripple and switching times as those of IDPWM while further reducing its overly large ZSCC, as validated by analytical results as well as experimental results. Since the proposed method obtains the optimal combination among switching loss, line current ripple, and maximum ZSCC peak, we name the proposed PWM scheme a high-performance DPWM.

Split-battery converters based on cascaded H-bridges (CHBs) are gaining popularity due to their excellent physical modularity. During operation, however, the batteries experience substantial current ripple. Conventional ripple-current reduction methods rely on bulky passive components or complicated control. This article presents modulation and common-mode voltage injection methods for cascaded double-H-bridge converters (CHB2). The control methods directly mitigate the source of the ripple current—the fluctuating arm power—by exploiting the parallel interconnection across the CHB2 arms. In the lab setup, the proposed solution approximately halves the battery current ripple compared to the CHB counterpart. Finally, this article studies component sizing and limitations of the proposed solution.

This article proposes a line-current ripple minimization pulsewidth modulation strategy with reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level converters. We split each 60° sector into six subsectors, each applies the nearest three vectors to ensure minimal line-current ripple. To reduce the ZSCC, we further investigate all vector sequences of the nearest three vectors and derive an optimal vector sequence for each of the six subsectors. We unify all carrier sequences under a carrier-based modulation scheme with the assistance of voltage injections. The injected voltage can be computed by a simple algorithm that allows easy implementation in mainstream microcontrollers. The experimental results validate that the proposed method maintains the minimal line-current ripple while significantly reducing the ZSCC compared to the existing line current ripple minimization methods.

When providing ac output, modular multilevel converters (MMCs) experience power fluctuation in the phase arms. The power fluctuation causes voltage ripple on the module capacitors, which grows with the output power and inversely to the output frequency. Thus, low-frequency operations of MMCs, e.g., for motor drives, require injecting common-mode voltages and circulating currents, and strict dc voltage output relative to ground is impossible. To address this problem, this paper introduces a novel module topology that allows parallel module connectivity in addition to the series and bypass states. The parallel state directly transfers power across the modules and arms to cancel the power fluctuations and hence suppresses the capacitor voltage ripple. The proposed series/parallel converter can operate at a wide frequency range down to dc without common-mode voltages or circulating currents; it also allows sensorless operation and full utilization of the components at higher output frequencies. We present detailed simulation and experiment results to characterize the advantages and limitations of the proposed solution.

Modules with series and parallel connectivity add new features and operation modes to modular multilevel converters (MMCs). Compared to full- and half-bridges, the series/parallel modules allow sensorless module balancing and reduce conduction loss with the same semiconductor area. However, in high-voltage applications with limited switching rates, the sensorless operation of the series/parallel modules suffers from large charge-balancing currents. This paper introduces a series/parallel module variant with a small port inductor. The port inductor suppresses the charge-balancing current despite low switching rates. We also propose a carrier-based modulation framework and show the importance of the carrier assignment in terms of efficiency and balancing. The proposed module and the modulation method are verified on a lab setup with module switching rates down to 200 Hz. The module voltages are kept within a narrow band with the charge-balancing currents below 5% of the arm current. The experimental results show practicality and advantages of the new series/parallel modules in high-voltage MMC applications.

Motor-evoked potentials (MEPs) are widely used for biomarkers and dose individualization in transcranial stimulation. The large variability of MEPs requires sophisticated methods of analysis to extract information fast and correctly. Development and testing of such methods relies on the availability for realistic models of MEP generation, which are presently lacking. This paper presents a statistical model that can simulate long sequences of individualized MEP amplitude data with properties matching experimental observations. The MEP model includes three sources of trial-to-trial variability: excitability fluctuations, variability in the neural and muscular pathways, and physiological and measurement noise. It also generates virtual human subject data from statistics of population variability. All parameters are extracted as statistical distributions from experimental data from the literature. The model exhibits previously described features, such as stimulus-intensity-dependent MEP amplitude distributions, including bimodal ones. The model can generate long sequences of test data for individual subjects with specified parameters or for subjects from a virtual population. The presented MEP model is the most detailed to date and can be used for the development and implementation of dosing and biomarker estimation algorithms for transcranial stimulation.

Cascaded H-bridge (CHB) converters are receiving growing attention in battery energy storage systems (BESS) due to their modularity and flexibility. However, direct generation of ac output in CHB-BESSs incurs large second-order current ripple in the batteries, which causes additional loss and might accelerate battery aging. Existing methods for ripple-current suppression usually require bulky passive components due to the high energy content of the ripple components. This paper presents a class of current injection methods for delta-configured CHB-BESSs. The injected currents flow through the CHB arms and transfer the original second-order oscillating power to the fourth or the sixth order, or even to an arbitrarily high-order frequency. As such, the battery current ripple appears at much higher frequencies with lower oscillating energy and can be easily filtered by small passive components. In the laboratory setup, the proposed methods reduced the battery root-mean-square current ripple to less than 10% of the dc component with negligible distortion in the loads. The proposed methods and the filter implementations show good tolerance to load frequencies and to the control error of the injected currents.

This paper presents a modular multilevel series/parallel converter (MMSPC) with intermodule switched-inductor power transfer. The switched-inductor voltage conversion feature allows controllable and efficient transfer of energy between modules with nonnegligible voltage difference, providing both step-down and step-up functionalities. Thus, this converter can accurately control and rapidly adjust the voltage of each module to generate an ac output voltage waveform with a controllable number of levels, increasing the quality of the output. Moreover, the intrinsic dc–dc conversion feature can generate a dc controllable output voltage and enable new applications. In this text, we specifically demonstrate how the flexibility of obtaining both ac and dc output with the same setup renders the topology promising for battery energy storage systems and dc microgrid applications. Experimental results validate the topology and concept of an MMSPC with intrinsic switched-inductor conversion.

This paper presents a multiobjective real-time controller for a modular multilevel converter capable of parallel module connectivity, the so-called modular multilevel series parallel converter (MMSPC). The MMSPC topology allows the batteries to be dynamically rewired in various series–parallel configurations, generating a wide range of output voltage levels. The novel control method parallelizes the modules to balance their voltages without the need for individual module voltage monitoring. Additionally, the controller optimizes across the large number of feasible system configurations to minimize switching and conduction losses. Finally, the controller efficiently encodes the system configuration with module interconnection states rather than the module switch states, which substantially simplifies control. Furthermore, this work experimentally validates the MMSPC topology and concept. In the prototype, the parallel mode reduced the system losses at 5 kW output power by 18% and 24% for load power factors of 1.0 and 0.8, respectively. Sensorless balancing via parallelization maintained well-matched module voltages (standard deviation = 0.045 V) over a 5-h battery discharge with highly variable load current. The reduced conduction losses and simple balancing capability of the MMSPC can enable new applications at medium and low voltages that benefit from its high-quality output, elimination of filtering magnetics, fast response, and modularity.

This paper introduces a novel modular multilevel series/parallel converter that allows switching modules dynamically not only in series, as in the traditional modular multilevel converter (M2C), but also in parallel. As in M2C, the semiconductor voltages do not exceed the module capacitor voltage for any module state. While the new topology is a generalization of M2C and could, therefore, be operated identically to it, the additional states provide degrees of freedom that the controller can dynamically employ to achieve several advantages. Whereas in M2C many modules are bypassed if the instantaneous converter voltage is lower than the system's peak voltage, the parallel connectivity enables these modules to contribute to the current load, thus reducing conduction losses. In addition, the parallel configuration of modules can be used for balancing the modules' state of charge (SOC). The parallelization losses are moderate or negligible, dependent on the switching rate. Since the parallel connection of capacitors can ensure balancing, it enables stable operation of a multilevel converter without the need for monitoring the module SOCs. While such economical control hardware may be appropriate for low-power systems, we also present more sophisticated control that uses the additional degrees of freedom to minimize losses. Finally, we point to further extensions of the circuit topology to multipole module connectivity that could enable additional functionality and applications.

Magnetic stimulation is gaining importance as an alternative to electrical stimulation in neurorehabilitation because it offers deep penetration and low pain. However, presently available equipment is not ideal for this purpose and sometimes even unsuitable. Furthermore, it is not known what physical conditions a coil has to provide for efficient stimulation. To solve these two problems, we set up a detailed 3-D computational model of the thigh to evaluate various coil designs with previously reported experimental performance. Comparison of the stimulation results with known experimental performance shows that a high absolute electric field seems to be sufficient for effective stimulation. Coil-generated field gradients, in contrast, do apparently not play a role. As a more appropriate metric, the electromagnetic coupling between different coil designs and the muscles of the thigh is found to be characteristic and explains the previously reported experimental performance differences. Furthermore, it is a good predictor for the achievable muscle torque (more than 99% correlation), whereas the gradient fails in this context. Accordingly, the model is able to test the performance of coils virtually and reveal both general relationships as well as design rules. In addition, the coupling factor formalism predicts a theoretical maximum level of the possible field induction and thus a guideline for potential improvements in the future.

This paper presents a novel method for fast and optimal determination of recruitment (input-output, IO) curve parameters in neural stimulation. A sequential parameter estimation (SPE) method was developed based on the Fisher information matrix (FIM), with a stopping rule based on successively satisfying a specified estimation tolerance. Simulated motor responses evoked by transcranial magnetic stimulation (TMS) were used as a test bed. Performance of FIM-SPE was characterized in 10 177 simulation runs for various IO parameter values corresponding to different virtual subjects, compared with uniform sampling. Unlike uniform sampling, FIM-SPE identifies and samples the areas of the IO curve that contain maximum information about the curve parameters. For the most relaxed stopping rule, the median number of samples required for convergence was only 17 for FIM-SPE versus 294 for uniform sampling. For the highest reliability stopping rule, more than 92% of the FIM-SPE runs converged, with a median of 88 samples, whereas all uniform sampling runs reached 1000 samples without converging. Compared to uniform sampling, FIM-SPE reduced estimation errors up to two-fold and required ten times fewer stimuli. FIM-SPE could improve the speed and accuracy of determination of IO curves for neural stimulation. A software implementation of the algorithm is provided online.