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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF $((2^{2})^{2})$ , is reduced. The squaring and multiplication with constant $\lambda $ in GF $((2^{2})^{2})$ are combined and optimized as well. Moreover, the multiplicative inversion in GF $((2^{2})^{2})$ is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

Conventionally, decimation-in-time (DIT) data-flow-graph (DFG) is used to obtain computing structures for discrete Hadamard transform (DHT). The fixed-width structures based on conventional approach, however, offers a marginal bit-saving and introduces relatively more truncation error. In this paper, we have derived decimation-in-frequency (DIF) DFG for DHT which is more convenient for approximation using truncation than the DIT-DFG. To achieve higher bit-saving with relatively less truncation error, we propose an efficient truncation model comprising of pre-truncation ( $\delta $ ) and post-truncation ( $\gamma $ ). Also, we present a logic optimized adder-subtractor design customized for DHT structure. Using the proposed truncation model, we have three variants of proposed structures for parallel computation of 2D DHT. The proposed structure-2 for DHT size $N=8$ , word-size $w=8$ , and approximation $(\delta _{1}=2, \gamma _{1}=1, \delta _{2}=2, \gamma _{2}=1)$ involves nearly 38% less area-delay-product (ADP) and 46% less energy per sample (EPS), and calculates outputs with almost the same accuracy as the existing fixed-width structure based on post-truncation. For the same word-size and $N=16$ , the proposed structure-2 for approximation $(\delta _{1}=2, \gamma _{1}=2, \delta _{2}=2, \gamma _{2}=2)$ involves nearly 36% less ADP and 44% less EPS than the existing structure and calculates outputs with the same accuracy. We have observed that reconstructed images obtained using the proposed structure-2 are less by 7 dB and 2 dB PSNR than those obtained using the existing fixed-width structures for $N=8$ and 16, respectively.

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel.

With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra- and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the “all-intra” configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.

This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard’s filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multistandard DUC.

A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.

Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4x4 16-QAM system, the area increases by 57% and the operating frequency degrades by 34% only.

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-mum standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance.

In this brief, a low-cost technique to implement variable-length coding (VLC) is presented. Instead of using a large codeword table as with most traditional methods, we employ two smaller tables, symbol-address table and section-based table, to encode input symbols. Compared with previous methods, our VLC implementation can reduce about 17% to 38% of memory space for storing larger VLC tables in MPEG-4 application. Synthesis results show that the proposed VLC encoder and decoder occupy 19761 and 20187 gate counts, respectively.

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 /spl mu/m CMOS technology and requires only 150 k gates for a total area of 1.5 mm/sup 2/ consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.

This paper proposes a polynomial search (PS) algorithm and architecture to solve the motion estimation problem in video coding. Simulation results show that the proposed method is not only flexible, but also requires fewer computations to achieve the same mean absolute error results (for QCIF and sub-QCIF video) compared with the existing fast-search algorithms. Finally, a VLSI architecture is also developed to efficiently implement the PS algorithm.

A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image.

A technique for number comparison in the residue number system is presented, and its theoretical validity is proved. The proposed solution is based on using a diagonal function to obtain a magnitude order of the numbers. In a first approach the function is computed using a suitable extra modulus. In the final implementation of the technique the extra modulus has been inserted in the set of moduli of the residue system, avoiding redundancy. The technique is compared with other approaches. >

In the above titled paper (ibid., vol. 54, no. 9, pp. 770-774, Sep. 07), equation (1) was incorrect. The correct equation is presented here.

Motivated by a growing demand for an efficient motion compensated (MC) coder operating in real time, the authors propose a VLSI architecture based on parallel and pipelined processing for implementing the pel-recursive motion estimation algorithm for predictive coding of time-varying images. In order to maximize the processing concurrency, the displacement estimation process is divided into its integer and fractional part calculations, and the displacement estimation and the interpolation calculations are decoupled so that each calculation can be computed on a separate processor. The proposed architecture, which exploits pipelining, parallelism, and simple adjacent-neighbor interprocessor wiring, is appropriate for VLSI implementation. The performance of the proposed architecture on the real image sequences is evaluated. Issues regarding the fixed-point arithmetic and coding are discussed. >

D channel processing in an ISDN exchange termination is very expensive using commercially available serial communications devices. This is because semiconductor manufacturers understand ISDN from the perspective of a terminal which is different from that of a network: the former sees one D channel, whereas the latter must deal with many. Consequently, commercially available devices are designed to support a small number of channels, whereas exchange terminations must cost-effectively support a large number of channels. This paper describes an innovative VLSI architecture that uses multiplexing to allow many channels to share serial communications circuitry as well as external message buffering. This capability will greatly reduce the hardware cost and complexity of D channel processing in ISDN exchange terminations.

The authors propose a VLSI architecture consisting of m*n processing elements with extensive parallel and pipelining computational capabilities. The worst-case time complexity is reduced to O(max(m, n)), which is a significant improvement over the uniprocessor approach. The algorithm partition problem, an important issue in VLSI design, and the verification of the proposed architecture are also studied. A series of experiments conducted to verify the proposed algorithms is described. >

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained. >