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There has been an impressive increase in single-chip processing power since the Intel 4004 was launched in 1971. This is usually attributed to Moore's law, but there are additional factors to consider. In understanding the components of prior improvements, we can gain insight into the potential for future improvements and potential limits to scaling.

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal–silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion.

A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, utilizing a per-bit silicon area of less than 350 $\mu \text{m}^{2}$ . Although such very small area allows for embedding in dense configurable fabrics (field-programmable gate arrays) and wafer-scale integration, the overall performance is not sacrificed as reported measurements show a signal-to-noise ratio of 51.87 dB and a spurious-free dynamic range of 42.31 dB, at 10 MS/s providing 7.6 effective bits. Moreover, the proposed architecture benefits from dynamic calibration capabilities, as any converter output can be finely adjusted over a range of 25 mV. This proposed DAC is also extensively reused in the same defect-tolerant network for a successive approximation register-analog-to-digital converter, as well as for a configurable voltage reference.

A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

Vacuum gap λ/2 microwave resonators are demonstrated as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Creating low loss circuits in this geometry is also discussed.

The articles in this special section report on the technologies and events that were part of the 31st Annual Hot Chips symposium was held at Stanford University in August 2019.

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.

A high-precision Cu–Cu bonding system for 3-D ICs (3-DICs) fabrication adopting a new precision alignment methodology is proposed. A new pressure profile control system is applied in the thermocompression bonding process. Experimental results show that the alignment capability is 250 nm or better, with similar overlay accuracy ( $\vert $ average $\vert + 3\sigma )$ for permanent bonding. These developments are expected to contribute to the fabrication of future 3-DICs.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology.

This article surveys recent work in optical switching technologies and presents a fast optical circuit switch that intimately integrates the control electrics at the chip level using a novel wafer-scale heterogeneous integration technique.

We propose an optical method to quantify the level of fabrication imperfections in a Silicon On Insulator wafer. The method is based on the use of Side Coupled Integrated Spaced Sequence of Resonators (SCISSOR) as test devices. Fabrication induced fluctuations of the effective index and of the coupling coefficient are mapped by comparing different spectral responses of nominally identical samples taken from different dies in the wafer. Random variations of the resonator's optical path are quantified in terms of standard deviations of normally distribuited variables by finding a statistical correlation with the coupled resonator induced transparency (CRIT) phenomena. We found a strong correlation between CRIT and fabrication errors. This led us to design a SCISSOR based test structure that allows to quantify the degree of local structural imperfections in a fast, accurate and non invasive way. Performances, possible applications and limitations are investigated with the help of transfer matrix simulations.

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.

Differential on-chip microstrip and slot-ring antennas with a quartz superstrate are presented for wafer-scale silicon systems. The antennas are fed at the nonradiating edge, which is compatible with differential coupled-lines, and are built on a 0.13-μ m CMOS process with a layout that meets all the metal density rules. A high radiation efficiency is achieved using a 100- μm quartz superstrate placed on top of the silicon chip. Both antennas have a measured gain varies from about 2 to 3 dBi at 91-94 GHz, with a - 10-dB S11 bandwidth of 7-8 GHz and a simulated radiation efficiency of >;50%. The designs are compatible with single- and multielement transceivers, and with wafer-scale imaging systems and power-combining arrays.

Silicon substrates form the foundation of modern microelectronics. Whereas the first 50 years of silicon wafer technology were primarily driven by the microelectronics industry, applications in photovoltaics (PV) also promise to drive new advances in silicon wafer technology over the next ten years. In the first part, we review the historical development of semiconductor silicon wafer technology and highlight recent technical advances in bulk crystal growth and wafering technologies, including the development of silicon-on-insulator (SOI) technologies and ultrathin wafers. We then discuss technologies that could take us beyond the current capabilities of complementary metal-oxide-semiconductor (CMOS) devices. In the second part, we review silicon manufacturing for PV applications and some unique wafering technology challenges in that field. Finally, we summarize industry roadmaps and product needs highlighting key technical areas which promise to shape the future of silicon wafer technologies in the coming decades.

What is the future of integrated inductor design on silicon for power conversion applications at frequencies up to 100 MHz-is it magnetic-core or air-core inductors. This study presents measured results for two microfabricated inductors (magnetic core and air core), which have been designed to operate at 20 MHz and occupy a substrate area of less than 10 mm2. The inductor technology and design are briefly discussed. An optimized inductor design study is, then, presented. Both magnetic-core and air-core inductor designs are compared and evaluated, in terms of inductance and efficiency per unit area for frequencies up to 100 MHz. The design of the microinductors is discussed and an analytical design optimization program is used to model the devices for the maximum efficiency and inductance. The introduction of laminations with high-frequency core inductors will also be examined within the study. A 100 MHz magnetic-core inductor design with three laminations gives a 36 nH inductance, with 96.4% efficiency and an area of 3 mm2 . A comparable air-core design also gives a 36 nH inductance, with 93.45% efficiency and an area of just 2.6 mm2.

This paper presents on-chip slot-ring and horn antennas for wafer-scale silicon systems. A high efficiency is achieved using a 100-μm quartz superstrate on top of the silicon chip, and a low-loss microstrip transformer using the silicon back-end metallization. A finite ground plane is also used to reduce the power coupled to the TEM mode. The slot-ring and 1-λ02 horn achieve a measured gain of 0-2 and 6-8 dBi at 90-96 GHz, respectively, and a radiation efficiency of ~50%. The horns achieve a high antenna gain without occupying a large area on the silicon wafer, thus resulting in a low-cost system. The designs are compatible with either single- or two-antenna transceivers, or with wafer-scale imaging systems and power-combining arrays.

System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for miniaturization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of system-in-package faces two critical issues: the management of components from different sources and the cost of individual operations necessary to complete the package. Taking into account all the developments that have been made to date on wafer level packaging (WLP), it has been proposed to perform the packaging system at wafer level. Fully tested bare dice are integrated onto or into a wafer which can be pre-processed and post-processed using techniques such as micromachining, passive integration, plating of via and pad redistribution, bumping, dicing and testing. The principal objective of this paper is to present alternative technology for integrated dice coming from various foundries where design, die thickness and contact pad metallurgy are predefined. System integration at wafer level is presented and discussed in this paper. Different approaches, such as system-on-wafer (SoW) or rebuilding a wafer, are introduced and a technology status report is drawn up.

This paper reports development of an in-situ metrology tool for monitoring metal contaminants existing in the semiconductor wafer cleaning process. Simultaneous detection of aluminum and transition metals at different wavelengths without significant interferences was made possible spectroscopically, using a mixture of 4-2- (pyridylazo) resorcinol and eriochrome cyanine red chelating reagents. This novel technology and apparatus designed for the fully automated in-situ metrology system enabled quantitative analysis of metal contaminants, even at sub-ppb concentrations. The metal monitoring technology is expected to be highly useful not only in semiconductor fabrication but also in several other industrial and academic fields.

Gigascale integration (GSI) chips with high bandwidth, integrated optoelectronics (OE), and photonic components are an emerging technology. In this paper, we present the prospects and opportunities for wafer-testing of chips with electrical and optical I/O interconnects. The issues and requirements of testing OE-GSI ICs during high-volume manufacturing are identified and discussed. Two probe substrate technologies based on microelectromechanical systems (MEMS) for simultaneously interfacing with a multitude of surface-normal optical I/Os and high-density electrical I/Os are detailed. The first probe substrate comprises vertically compliant probes for contacting electrical I/Os and grating-in-waveguide I/Os for optical probing. The second MEMS probe module uses microsockets and through-substrate interconnects to contact pillar-shaped electrical and optical I/Os and to redistribute signals, respectively.

A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.

Through-silicon-via (TSV) interconnects using the "via-last" approach are successfully applied for wafer-level packaging of complementary metal-oxide-semiconductor (CMOS) image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening, and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer-level packaging process for optical and M(O)EMS devices.

With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-?P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.

Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain-bandwidth product of 40-130 GHz and low frequency gain > 45 dB . The use of InP DHBTs supports a > 6.9 V differential output swing and a slew rate > 4 times 104V/mus to be achieved with as low as 40 mW dissipated power. A novel on-chip buffer circuit is used to facilitate the on-wafer characterization of these amplifiers. To the authors' knowledge, this is the first demonstration of a high performance IC building block in a heterogeneously integrated process technology.

In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13% reduction in thermal resistance.

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.

In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, -40degC ~ 125degC). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications.

We have developed a novel all SU-8 packaging method for microelectromechanical system (MEMS) devices. The process is low temperature and low cost and it allows for nonhermetic as well as hermetic packaging. The nonhermetic package can be applied to sensors. The process flow is based on a partial and a full exposure of SU-8 negative resist using two masks. The underexposed region results in cross-linking of only a surface layer, while the underlying resist is not cross-linked and can be removed using SU-8 developer. By depositing a second SU-8 layer a sealed package for MEMS devices can be achieved. The packaging method provides any pattern and cavity clearance since it is solely based on lithography steps. The concept of the packaging method is introduced in this paper and then its practical validity demonstrated using simulation and characterization results.

A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal ldquobig-D/small-Ardquo SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100-mum pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of ~ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.

In this paper, we describe a new wafer yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.

This paper validates a proposed job release methodology and experimentally investigates the impact of production control methodologies and system factors on wafer fab performance in terms of average cycle time, standard deviation of cycle time, average lateness, WIP inventory and fab output by simulating a wafer fab of Chartered Semiconductor Manufacturing Ltd (Chartered) and statistically analyzing the experimental results using t-test and ANOVA. A full factorial design of experiment is conducted to evaluate the performance of three job release methodologies, three dispatching rules and three greedy levels of batching policy under different system environmental settings differentiated by fab output level and machine unreliability level. Based on the experimental results, the proposed job release methodology WIPLOAD control (WIPLCtrl) appears to be very efficient to be able to potentially improve all the considered performance measures simultaneously. The advantage of WIPLCtrl is robust to the change of system environmental conditions. In contrast, the improvement brought by a dispatching rule on a certain performance measure might cost the deterioration of other performances. Considering the relative impact on the fab performance, job release control appears to be the most important production control factor in comparison with dispatching and batching policy, especially when the system is operating on a high output level and/or with a high system variability level caused by machine unreliability.

This paper reports a MEMS vacuum package with vertical feedthroughs formed in a glass substrate all at the wafer level. This approach satisfies requirements for MEMS vacuum packages, including small size, vacuum/hermetic capability, sealed and low parasitic feedthroughs, wafer-level processing, compatibility with most MEMS processes, and low cost. It also enables flip-chip solder attachment to a PC board. The package has an integrated micro-Pirani gauge on a glass substrate for in situ monitoring, a silicon cap, and vertical feedthroughs through the glass. The integrated Pirani gauge has 0.6 milli-torr resolution at 0.1 torr and 0.2 torr resolution at 100 torr. Using the Pirani gauge, the fabricated vacuum package is characterized. The package has maintained ~33 torr base pressure with plusmn1.5 torr uncertainty for more than four months without a getter. The long-term measured pressure uncertainty is from the measurement setup and environment, and can be improved using a getter inside the package. [2007-0160]

This paper presents a new implementation of integrated tunable inductors using mutual inductances activated by micromechanical switches. To achieve a large tuning range and a high quality factor, silver was used as the structural material, and silicon was selectively removed from the backside of the substrate. Using this method, a maximum tuning of 47% at 6 GHz is achieved for a 1.1 nH silver inductor fabricated on a low-loss polymer membrane. The effect of the quality factor on the tuning characteristic of the inductor is investigated by comparing the measured result of identical inductors fabricated on various substrates. To maintain the quality factor of the silver inductor, the device was encapsulated using a low-cost wafer-level polymer packaging technique.

We have developed a generic cost-efficient CMOS-compatible heterogeneous device integration method at wafer-scale level. This method enables the distribution of devices from one to numerous wafers using selective transfer technology. We have applied this method for the distribution of atomic force microscopy (AFM) cantilevers and successfully demonstrated the population of multiple wafers from one source wafer. The distribution function has been designed such as to populate 42 wafers with only one source wafer. This CMOS back-end-of-the-line compatible method is particularly suitable for microelectromechanical systems and integrated circuits. Electrical interconnects are compatible with this technology. We present the concept, the selective transfer method, including a laser ablation technique used for the transfer, as well as the process and results of the application for AFM cantilever distribution.

Solid state image sensors are increasingly being adopted for automotive applications. The harsh operating environment and requirement for long life means reliability standards for automotive components far exceed those of the normal sphere of use, namely mobile telephones. Electrophoretic paints are widely used in the automotive and construction industries to endow fabricated metal products with corrosion resistant, decorative, coatings. This paper describes the first known use of these materials for semiconductor packaging. The application is a wafer level packaging process to encapsulate image sensors, which will comfortably surpass the automotive standard for reliability.

Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is presented to decompose process variability using statistics of the measurements from manufacturing inline test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing inline parameters in 65-nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variation obtained with manufacturing inline parameters.

The planar process also made it easy to interconnect neighboring transistors on a wafer, paving the way to another Fairchild achievement: the first commercial integrated circuits. As other companies realized the great advantages of planar technology and began adopting it on their own production lines, Hoerni's elegant idea helped to establish Silicon Valley as the microelectronics epicenter of the world.

In this paper, we present the experimental results on wafer-to-wafer and within-wafer critical dimension (CD) control. It is known that photoresist thickness affects CD. In this paper, we control photoresist thickness to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real time and makes use of the current wafer information for control of the current wafer CD. The experiments demonstrate that such an approach can reduce CD nonuniformity wafer to wafer and within wafer.

Topography on the wafer surface has a great effect on chemical-mechanical polishing (CMP). In this paper, the performance of a CMP system is demonstrated to be approximately an linear time invariant (LTI) system. The effects of the low-frequency components and high-frequency components in the wafer topography on CMP process are investigated. The magnitude spectra and phase spectra of the system are obtained. A model for the effect of more complex topography is established based on Fourier transform. The influences of down force and pad stiffness on the performance of CMP with the same topography are also studied.

Some emerging microelectromechanical systems (MEMS) devices such as high-performance inertial sensors and high-speed actuators must be operated in a high vacuum and in order to create this vacuum environment, specific packaging is required. To satisfy this demand, this paper presents a novel method for hermetic and near-vacuum packaging of MEMS devices. We use wafer-level bonding technology to combine with vacuum packaging, simultaneously. For this packaging solution, the wafers with air-guided micro-through-holes were placed on a custom-built design housed in a vacuum chamber maintained at a low-pressure environment of sub-10 mtorr. Packaging structure is then sealed by solder ball reflow process with the lower heating temperature of 300degC to fill up micro-through-hole. Experimental results shown the hermetical packaging technique using solder sealing is adapted to the wafer-level microfabrication process for MEMS devices and can achieve better yield and performance. Thus, this technique is very useful for many applications with high performance and low packaging cost can be obtained due to wafer-level processing.

Semiconductor wafer fab operations are characterized by complex and reentrant production processes over many heterogeneous machine groups with stringent performance requirements. Efficient composition of good scheduling policies from combinatorial options of wafer release and machine dispatching rules has posed a significant challenge to competitive fab operations. In this paper, we design a fast simulation-based methodology by an innovative integration of ordinal optimization (OO) and design of experiments (DOEs) to efficiently select a good scheduling policy for fab operations. Instead of finding the exact performance among scheduling policies, our approach compares their relative orders of performance to a specified level of confidence. Our new approach consists of three stages: performance estimation model construction using DOE, policy option screening process, and final simulation evaluation with intelligent computing budget allocation. The exponential convergence of OO is integrated into all the three stages to significantly improve computational efficiency. Simulation results of applications to scheduling wafer fabrications not only screen out good scheduling policies but also provide insights about how factors such as wafer release and the dispatching of each machine group may affect production cycle times and smoothness under a reentrant process flow. Most of the OO-based DOE simulations require 2-3 orders of magnitude less computation time than those of a traditional approach. Such a high speedup enables decision makers to explore much larger problems. Note to Practitioners - This paper designs a fast simulation-based methodology to compose a good scheduling policy from various dispatching rules of fab operations. The methodology innovatively applies DOE to estimate performance of dispatching rule combinations (policies) over various machines groups in a fab, screens out good enough policy options by using OO over the performance estimation, and allocates computation time intelligently to simulate potentially good options. Our study shows that OO-based DOE simulations require 2-3 orders of magnitude less computation time than those of a traditional approach. The high speedup enables fab managers to identify good scheduling policies from the many combinations of wafer release and dispatching rules.

In this paper, we present the development of disposable single-use microfluidic pumps entirely based on a straightforward wafer-level fabrication scheme, which allows for precise integrated active dosing in the microliter range. To accomplish stroke-lengths needed for microliter-range applications, we utilize a new method of bending of a unimorph-composite-actuator film. The unimorph composite actuator consists of a temperature-sensitive silicone elastomer composite, i.e., polydimethylsiloxane, with incorporated expandable microspheres. The fabricated micropumps successfully demonstrated precise liquid-volume control, both at low and high flow rates, and show a standard deviation of 6.7% for consecutive pump experiments. Moreover, the method of fluorescent thermometry was used to measure the thermal load on liquid volumes dispensed with the micropumps. The liquid temperature reaches a maximum of 50degC during the operation. The presented fully integrated single-use micropumps are electrically controllable, do not require external means for liquid actuation, are made of low-cost materials only, and might potentially be used in drug-delivery applications.

We describe a low-temperature polymer-based 3D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 oC. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3D inverter circuit along with demonstration of four-device-layer 3D integrated stack are presented.

Multichip integration provides an attractive means to overcome space limitations for large-port-count optical microelectromechanical systems (MEMS) routing systems by allowing actuation and control wiring to be fabricated separately on one chip and then attached beneath a second chip that is populated with a densely packed mirror array. In such systems, vertical as well as horizontal chip alignment is critical when a large but very uniform separation must be maintained across the extent of the array. A technique for creating a structure that simultaneously provides accurate large-gap spacing and acts as a chip-bonding agent is presented here. Specialized processing of an 80- mum thick photoimaged polyimide structure for bonding mirror and electrode chips for a 1296-mirror array is described, along with measurements of height uniformity within 1% and structure characterization demonstrating suitability for production and long-term stability. The process parameters and simplicity of the technique make it suitable for a wide range of applications where MEMS must be integrated with electronic control circuitry. [2006-0042].