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This paper focuses on a lot merging-splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging-splitting algorithms to reduce the total tardiness of the orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab.

In this paper, we consider a scheduling problem in a semiconductor test facility. We focus on the burn-in workstation and its corresponding loading/unloading workstation, which may be considered bottleneck workstations in the test facility. In the burn-in workstation, there are parallel identical batch-processing machines, called chambers, while there are unrelated parallel machines in the loading/unloading workstation. We present heuristic algorithms for the scheduling problem at the burn-in workstation as well as the loading/unloading workstation with the objective of minimizing total tardiness of orders. For evaluation of performance of the algorithms, a series of computational experiments are performed on a number of problem instances, and results show that the suggested heuristic algorithms outperform existing scheduling rules that are currently used in a real system.

This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice.

This paper focuses on a production planning and scheduling problem in a semiconductor wafer fabrication facility. We propose a two-level hierarchical production planning (HPP) method that employs an itmmerative procedure for production planning and operations scheduling. In the method, production plans are obtained with a linear programming (LP) model in the aggregate level, and schedules at the machines are obtained with a priority-rule-based scheduling method and evaluated with discrete-event simulation in the disaggregate level. An iterative scheme is adopted for obtaining a good and feasible production plan. The proposed method is evaluated through simulation experiments and the results show that the method works better than an existing algorithm in terms of the total production cost and total tardiness of orders.

This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy.

This paper presents a real-time scheduling methodology in a semiconductor wafer fab that produces multiple product types with different due dates. In the suggested real-time scheduling method, lot scheduling rules and batch scheduling rules are selected from sets of candidate rules based on information obtained from discrete event simulation. Since a rule combination that gives the best performance may vary according to the states of the fab, a selected rule combination is employed for a certain period of time and then a new combination is selected and employed. Since multiple simulation runs should be made in the simulation-based real-time scheduling (SBRTS) method, it may take excessively long computation time to react to unexpected events. To reduce response time, we suggest three techniques for accelerating rule comparison. We test these techniques as well as other operational policies that can be used in the SBRTS method through computational experiments on a number of test problems.

Focuses on production scheduling in a semiconductor wafer fab producing multiple product types that have different due dates and different process flows. In the wafer fab, wafer lots are processed on serial and batch processing workstations, each of which consists of parallel identical machines. Machines in serial processing workstations process wafer lots one by one, while those in batch processing workstations process several wafer lots of the same recipe at the same time. What needs to be done for production scheduling are lot release control, lot scheduling, and batch scheduling. For these three decision problems, we develop several rules which use information such as order sizes (numbers of lots in orders) and processing status of the wafer lots. To evaluate these new rules, we use a simulation model in which the three decision problems are considered simultaneously. Simulation results show that the new rules work better than existing rules in terms of total tardiness of the orders.

This paper considers a tool provisioning problem in a flexible manufacturing system (FMS) with an automatic tool transporter. The problem considered here is that of determining the number of copies of each tool type for a limited budget with the objective of minimizing makespan. This problem should be solved to decide the (additional) purchase of required tools when the FMS should be reconfigured due to change of part mix. To solve the problem, two heuristic algorithms are proposed. One is a composite search algorithm based on two greedy search methods, and the other is a search algorithm in which numbers of tool copies are determined based on tool groupings. In both algorithms, simulation results are used to find search directions. Computational experiments show that the latter search algorithm gives better results.

This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of processing waiting lots in front of workstations for lot scheduling. New dispatching rules are developed for lot release control and scheduling considering special features of the wafer fabrication process. Simulation experiments are carried out to test the dispatching rules. Results show that lot release control and lot scheduling at photolithography workstations are more important than scheduling at other workstations. Also, it is shown that new dispatching rules work better in terms of tardiness of orders than existing rules such as the EDD (earliest due date) rule and other well-known dispatching rules for multimachine scheduling.