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Due to the lack of end-to-end paths between the communication source and destination, the routing of Delay Tolerant Networks (DTN) exploits the store-carry-and-forward mechanism. This mechanism requires nodes with sufficient energy to relay and forward messages in a cooperative and selfless way. However, in the real world, the energy is constrained and most of the nodes exhibit selfish behaviors. In this paper, we investigate the performance of DTN routing schemes considering both the energy constraint and selfish behaviors of nodes. First, we model the two-hop relay and epidemic routing based on a two-dimensional continuous time Markov chain. Then, we obtain the system performance of message delivery delay and delivery cost by explicit expressions. Numerical results show that both the energy constraint and node selfishness reduce the message delivery cost at the expense of increasing the message delivery delay. Furthermore, we demonstrate that the energy constraint plays a more important role in the performance of epidemic routing than that of two-hop relay.

The influence of quantization scaling is seldom considered in narrow band (NB) communications, because a high resolution analogue-to-digital converter (ADC) can be generally employed. In ultra-wideband (UWB) systems, however, the resolution of ADC is required to be low to reduce complexity, cost and power consumption. Consequently, the influence of quantization scaling is significant and should be taken into account. In this letter, effects of quantization scaling are analyzed in terms of signal to noise ratio (SNR) loss based on an uniformly distributed random signal model. For the effects of quantization scaling on bit error rate (BER) performance, however, theoretical analysis is too complicated since quantization is a nonlinear operation, hence we employ here a simulation method. The simulation results show there exists an optimum scaling to minimize BER performance for a fixed-resolution receiver; the optimum scaling power is related to the SNR of input noisy signal and the resolution of ADC.

Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

To deal with the increasing number of mobile devices accessing the Internet and the increasing demands of mobility management, IETF has proposed Mobile IPv6 and its fast handover protocol FMIPv6. In FMIPv6, the possibility of Care-of Address (CoA) collision and the time for Return Routability (RR) procedure result in long handover delay, which makes it unsuitable for real-time applications. In this paper, we propose an improved handover scheme for FMIPv6, which reduces the handover delay by using proactive CoA acquisition, configuration and test method. In our proposal, collision-free CoA is proactively prepared, and the time for RR procedure does not contribute to the handover delay. Furthermore, we analyze our proposal's benefits and overhead tradeoff. The numerical results demonstrate that it outperforms the current schemes, such as FMIPv6 and enhanced FMIPv6, on the aspect of handover delay and packet transmission delay.

RAKE receivers are generally employed to collect multipath energy in single-carrier ultra-wideband (SC-UWB) systems and direct-sequence ultra-wideband (DS-UWB) systems. Performance of RAKE receivers in these two kinds of systems is studied and compared with each other in this letter. Both theoretical analysis and simulation results over IEEE 802.15.3a UWB channels are presented. Our results show that, with the same signal to noise ratio (SNR) per bit, the same occupied bandwidth and the same number of RAKE fingers, RAKE receivers with maximum ratio combination (MRC) in SC-UWB systems can achieve exactly the same performance as that in DS-UWB systems.

In network tomography, most work to date is based on exploiting probe packet level correlations to infer the link loss rates and delay distributions. Some other work focuses on identifying the congested links using uncorrelated end-to-end measurements and link prior probability of being congested. In their work, the prior probabilities are identified by the matrix inversion with a number of measurement snapshots, and the algorithm to find the congested links is heuristic and not optimal. In this letter, we present a new estimator for the prior probabilities that is computationally simple, being an explicit function of the measurement snapshots. With these prior probabilities, the identification of the congested link set is equivalent to finding the solution for a probability maximization problem. We propose a fast bottom-up approach named FBA to find the solution for this problem. The FBA optimizes the solution step by step from the bottom up. We prove that the solution by the FBA is optimal.

Since the length of wires between different layers, even between the top and bottom layers, is acceptably small in 3D mesh-based NoC (three-Dimensional mesh-based Network on Chip), a structure in which an IP (Intelligence Property) core in a certain layer directly connected to a proper router in another layer may efficiently decrease the average latency of messages and increase the maximum throughput. With this idea, in the paper, we introduce a dual-port access structure, in which each IP core except that in the bottom layer is connected to two routers in two adjacent layers, and, in particular, the IP core in the bottom layer can be directly connected to the proper router in the top layer. Furthermore, we derive the close form expression of the average number of hops of messages and also give the quantitative analysis of the performance when the dual-port access structure is used. All the analytical results reveal that the average number of hops is reduced and the system performance is improved, including a decrease of average latency and an increase of maximum throughput. Finally, the simulation results confirm our theoretical analysis and show the advantage of the proposed dual-port access structure with a relatively small increment of area overhead.

Single-carrier ultra-wideband (SC-UWB) is weak due to the problem of serious inter-symbol interference (ISI), which is generated in dense multipath with a long root-mean-square (RMS) delay spread. The selective RAKE (SRAKE) based RAKE-decision feedback equalizer (RAKE-DFE) receiver is usually employed to combat ISI in practical SC-UWB systems. Considering the system complexity, however, the number of RAKE fingers is usually small. In this case, conventional RAKE-DFE receivers can hardly collect enough energy to achieve a good performance. In this paper, the optimum SRAKE based RAKE-DFE receiver was proposed as a solution. Theoretical analysis and simulations are presented. Results and conclusions show that the proposed SRAKE scheme is optimum to collect energy of multipath. Moreover, the proposed RAKE-DFE receiver outperforms conventional RAKE-DFE receiver by about 1dB, but the complexity for them both is almost the same.

We present a recovery scheme based on Self-protected Spanning Tree (SST), which recovers from failure all by itself. In the recovery scheme, the links are assigned birthdays to denote the order in which they are to be considered for adding to the SST. The recovery mechanism, named Birthday-based Link Replacing Mechanism (BLRM), is able to transform a SST into a new spanning tree by replacing some tree links with some non-tree links of the same birthday, which ensures the network connectivity after any single link or node failure. First, we theoretically prove that the SST-based recovery scheme can be applied to arbitrary two-edge connected or two connected networks. Then, the recovery time of BLRM is analyzed and evaluated using Ethernet, and the simulation results demonstrate the effectiveness of BLRM in achieving fast recovery. Also, we point out that BLRM provides a novel load balancing mechanism by fast changing the topology of the SST.

Delay Tolerant Networks (DTNs) are able to provide communication services in challenged networks where the end-to-end path between the source and destination does not exist. In order to increase the probability of message delivery, DTN routing mechanisms require nodes in the network to store and carry messages in their local buffer and to replicate many copies. When the limited buffer is consumed, choosing appropriate messages to discard is critical to maximizingthe system performance. Current approaches for this are sub-optimal or assumed unrealistic conditions. In this paper, we propose an optimal buffer management scheme for the realistic situations where the bandwidth is limited and messages vary in size. In our scheme, we design a message discard policy that maximizes the message delivery rate. Simulation results demonstrate the efficiency of our proposal.

A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 μm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.

The LC-based Digitally Controlled Oscillator (DCO) is one of the most important components of all digital phase locked loops. The performance of the loops is significantly determined by the DCO's frequency resolution. In order to enhance the frequency resolution, we propose a mismatched capacitor pairs based digitally controlled switched capacitance array, which dramatically reduces the minimum switched varactor capacitance. Furthermore, we implement a DCO based on our proposal in SMIC 0.18 μm and conduct simulation in Spectre. The simulation results show that the frequency resolution is enhanced compared with the existing methods.

Based on the traffic predictability characteristic of Networks-on-Chip (NoC), we propose a pre-allocation based flow control scheme to improve the performance of NoC. In this scheme, routes are pre-allocated and the injection rates of all routes are regulated at the traffic sources according to the average available bandwidths in the links. Then, the number of packets in the network is decreased and thus, the congestion probability is reduced and the communication performance is improved. Simulation results show that this scheme greatly increases the throughput and cuts down the average latency with little area and energy overhead, compared with the switch-to-switch flow control scheme.

Motivated by different error characteristics of each path, we propose a study-based error recovery scheme for Networks-on-Chip (NoC). In this scheme, two study processes are executed respectively to obtain the characteristics of the errors in every link first; and then, according to the study results and the selection rule inferred by us, this scheme selects a better error recovery scheme for every path. Simulation results show that compared with traditional simple retransmission scheme and hybrid single-error-correction, multi-error-retransmission scheme, this scheme greatly improves the throughput and cuts down the energy consumption with little area increase.