16 results on '"Yu, Zhiyi"'
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2. A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations
3. A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS
4. An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks
5. Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks
6. DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing
7. A multi-core-based heterogeneous parallel turbo decoder
8. Non-binary digital calibration for split-capacitor DAC in SAR ADC
9. An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing
10. Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65nm CMOS
11. Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform
12. Design of a high information-density multiple valued 2-read 1-write register file
13. A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform
14. A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS
15. A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs
16. A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue
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