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This study proposes a novel network sensitivity-based approach to solving complex power flow calculation problems in real time. A new sensitivity factor, named Jacobian-based distribution factor (JBDF), is used for the calculation of active and reactive power flow in transmission systems. It is derived from the Jacobian matrix of the base case Newton-Raphson power flow solution, and kept constant during real-time line flow calculation. Unlike well-known distribution factors, such as generation shift distribution factor (GSDF), generalised generation shift distribution factor (GGDF) and Z-bus distribution factor (ZBD), this approach reflects changes in complex injection power. Changes in load conditions from base case loads, with either conforming or non-conforming changes in complex power in each bus, can be used to rapidly compute active and reactive power flow without iterations. The proposed approach was tested on IEEE 14-Bus and 30-Bus systems. Numerical results demonstrate that the proposed approach is not only superior to previous distribution factors, but also compares favourably with the Newton-Raphson power flow method. It is well suited to real-time applications in steady-state security control and optimal dispatch. [ABSTRACT FROM AUTHOR]

Finite field arithmetic has been widely used in many cryptosystems, particularly in the elliptic curve cryptosystem (ECC) and the advanced encryption standard (AES) as a method for speeding up their encryption/decryption processes. Low-cost design for finite field arithmetic is more attractive for various mobile applications. It is a factor that a large number of Exclusive OR (XOR) gates have been used in the arithmetic operations under the traditional finite field arithmetic implementation. Thus, the cost of the traditional finite field arithmetic cannot be effectively lowered, because a typical XOR gate design consists of 12 transistors. To address this, a novel non-XOR approach consisting of eight transistors, for realising low-cost polynomial basis (PB) multiplier over GF(2m) was developed in this study. The authors proposed that non-XOR architecture for bit-parallel PB multiplier uses the multiplexer function instead of the traditional XOR function in its design. Based on the proposed non-XOR methodology, three popular low-cost irreducible polynomials - trinomial, pentanomial and all-one-polynomial - are proposed and designed in this study. The results indicate that the proposed non-XOR architecture can reduce space complexity by 22%, compared with that of the traditional design. [ABSTRACT FROM AUTHOR]

Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. Fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author's knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability. [ABSTRACT FROM AUTHOR]

Presented are the effects of a guard trace with the optimal number of grounded vias that gives maximum efficiency for preventing crosstalk in parallel double micro-strip lines in a high-speed printed circuit board layout. Compared to a guard trace with two terminal grounded vias, the near-end crosstalk is reduced from 95 to 30 mV and the far-end crosstalk is reduced from 121 to 56 mV. [ABSTRACT FROM AUTHOR]