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A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area. [ABSTRACT FROM AUTHOR]

A comparator-based buffer is proposed to enhance the driving capability of high-gain amplifiers with switched-capacitor loads. A simple correction scheme using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage. SPECTRE simulations verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power. [ABSTRACT FROM AUTHOR]

A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC. [ABSTRACT FROM AUTHOR]

A double-sampled delta-sigma (ΔΣ) modulator topology is proposed that can relax the critical timing constraints in the modulator feedback path. The speed requirements of the quantiser and dynamic element matching logic are thus greatly reduced. To verify the effectiveness of the proposed topology, a second-order double-sampled ΔΣ modulator is designed and simulated. [ABSTRACT FROM AUTHOR]

A scheme is proposed for adjusting the bias current of the op-amp in a switched-capacitor stage so that it follows the swing of the input signal, minimising the power consumption of the stage. Simulations indicate that a 60% power saving is possible using the method. [ABSTRACT FROM AUTHOR]

A split Δ-Σ ADC topology is proposed which provides enhanced noise shaping by cross-coupling the quantisation errors of the two halves of the structure. Unlike the multi-stage noise shaping architecture, the new structure is insensitive to mismatch errors and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

A high-precision switched-capacitor integrator using a low-gain opamp is proposed. The circuit contains a main signal path and a predictive signal path which makes the correlated double sampling more effective. The proposed integrator was simulated using SPICE parameters for a 180 nm CMOS process with a supply voltage of 1.2 V. The circuit exhibited much lower harmonic distortion than those described in earlier works. [ABSTRACT FROM AUTHOR]

A new tuning technique is proposed for Gm-C filters. The transconductance cells are tuned using switched resistors (SRs), which change the equivalent reference resistance of each cell. In the tuning circuit, the equivalent resistance of an SR branch is forced to equal that of a switched-capacitor (SC) branch by a feedback loop containing a continuous-time comparator. Thus, using the output of the loop all time constants of the Gm-C filter can be tuned simultaneously. The simulation of a second-order Butterworth filter is described to verify the effectiveness and excellent linearity of the proposed tuning method. [ABSTRACT FROM AUTHOR]

Two new start-up DAC calibration techniques are proposed for double-sampling ΔΣ modulators. The first one is a modification of the existing calibration technique, while the second technique is proposed specifically for double-sampling ΔΣ modulators. Dynamic element matching is used to eliminate ‘intra-DAC’ mismatches, and digital correction for the remaining ‘inter-DAC’ mismatches. [ABSTRACT FROM AUTHOR]

The low-distortion modulator is an effective ΔΣ ADC architecture for high-linearity and low-dissipation applications. However, it has several practical drawbacks. An improved low-distortion modulator topology that avoids these disadvantages is suggested. [ABSTRACT FROM AUTHOR]

The noise-coupling technique successfully used in discrete-time delta-sigma analogue-to-digital converters (ADCs) is extended to the realisation of continuous-time delta-sigma ADCs, resulting in improved quantisation noise shaping. To verify the proposed design methodology, a second-order continuous-time delta-sigma modulator with noise coupling is designed and simulated. [ABSTRACT FROM AUTHOR]

A single-loop delta–sigma modulator with extended dynamic range is proposed. It employs an auxiliary quantiser to process the quantisation error of the main quantiser. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. Simulation results are provided to verify the effectiveness of this structure. [ABSTRACT FROM AUTHOR]

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not require bilinear integration. It allows the use of efficient design methods for ΔΣ ADCs. [ABSTRACT FROM AUTHOR]

The first-order noise coupling scheme proposed earlier is generalised to the realisation of higher-order enhancement. It is also extended to single-stage ΔΣ loops, and to split structures with self-enhancement. The advantages and limitations of these new ΔΣ architectures are compared with those of conventional single-stage and cascade ΔΣ structures. As demonstrated by an example, they exhibit improved stability and robustness under practical fabrication conditions. [ABSTRACT FROM AUTHOR]

A modified dynamic element matching algorithm, based on splitting the unit element set into subsets, is proposed. Simulations show that it can improve the spur-free dynamic range of data-weighted averaging significantly, without degrading its signal-to-noise ratio. [ABSTRACT FROM AUTHOR]