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A compact planar Wilkinson power divider is proposed using two-section asymmetrical T-structures to achieve a significant size reduction and retain a mimic return-loss bandwidth as compared with the conventional one. The asymmetrical T-structure is realised by two series high-impedance lines with unequal electrical lengths and a shunt low-impedance line. The two-section configuration has the advantage of decreasing the shunt stub size, and then achieving an optimally miniaturised circuit layout. The developed power divider has a 66.5% 15 dB return loss bandwidth and only occupies a 12.7% circuit size of the conventional one. The measured results of the developed power divider are in a good agreement with simulated results.

A current-mode full-wave rectifier and current-mode vector summation circuit are presented. They are implemented by utilising the square-law characteristics of MOS transistors in saturation. A two-input vector summation circuit using the proposed full-wave rectifier has been fabricated in a 0.8 /spl mu/m CMOS process. The experimental and simulation results confirm the feasibility of the proposed circuits.

A current-mode pseudo-exponential circuit is presented based on Taylor's series expansion. It is composed of MOS transistors operating in saturation and its input range can be tuned by adjusting the biased current. The proposed circuit has been verified in 0.8 /spl mu/m CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed pseudo-exponential circuit.

A BiCMOS squarer using active attenuators which has been fabricated in a 10 /spl mu/m BiCMOS process is presented. Experimental results show that the nonlinearity of the squarer can be kept below 2%, across the entire input voltage range of /spl plusmn/0.3 V. Its -3 dB bandwidth is measured to be /spl sim/1 MHz. Moreover, based on the proposed squarer circuits, a four-quadrant multiplier and a vector summation circuit have also been realised. The proposed circuits are expected to be useful in analogue signal processing applications.

A four-quadrant multiplier and a two-quadrant divider are presented. The proposed circuits are implemented by MOSFETs operating in weak inversion and are therefore suitable for low voltage and low power applications. Their performances were confirmed by HSPICE simulation using a 0.8 /spl mu/m CMOS process. The multiplier can operate under a /spl plusmn/0.75 V supply voltage and its linear input range is /spl sim/0.125 /spl mu/A with error