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Reed–Solomon (RS) codes possess excellent error correction capability. Algebraic soft-decision decoding (ASD) of RS codes can provide better correction performance than the hard-decision decoding (HDD). The low-complexity Chase (LCC) decoding has the lowest complexity cost and similar or even higher coding gain among all of the available ASD algorithms. Instead of employing complicated interpolation technique, the LCC decoding can be implemented based on the HDD. This study proposes a modified serial LCC decoder, which employs a novel syndrome calculation, polynomial selection, Chien search and Forney algorithm block. In addition, an improved two-dimensional optimisation is provided to reduce the hardware complexity of the proposed decoder. Compared with the previous design, the proposed decoder can improve about 1.27 times speed and obtain 1.29 times higher efficiency in terms of throughput-over-slice ratio.

A fast, area efficient very large scale integration (VLSI) architecture is proposed for a unique decoding algorithm of Hermitian codes which was presented recently by Lee and O'Sullivan from an interpolation perspective. The algorithm iteratively computes the sent message through a majority voting procedure by using the Grobner bases of interpolation modules. The algorithm has a regular structure which makes it suitable for VLSI implementation. The circuitry is simplified as the decoding algorithm directly gives the message word at the end of the decoding algorithm without separate steps like Chien search and Forney's formula. In terms of hardware requirements, for the widely used high rate Hermitian codes, the Lee–O'Sullivan algorithm is q times faster than Kotters algorithm with the same space complexity of O(q 4). Further speed improvements can be achieved by combining the main idea of Guruswami list decoding with the Lee–O'Sullivan algorithm. In terms of hardware, the addition of this concept, will further reduce the running time of the algorithm and make the circuitry about two times faster than the original Lee–O'Sullivan algorithm. The implementation results for both the Koetter and the Lee–O'Sullivan algorithms on Xilinx Virtex-5 shows that the proposed decoder can be operated at higher clock frequency with almost same area complexity.

A Lee-metric list-decoding algorithm for Reed–Solomon (RS) codes over GF( p) is presented. The algorithm is obtained by generalising the Guruswami–Sudan (Hamming metric) list-decoding algorithm for RS codes. The algorithm can be used to decode the Lee-metric BCH codes, and outperforms the known Lee-metric decoding algorithm for BCH codes.

A Grobner basis algorithm for errors-and-erasures decoding of BCH codes that avoids computation of the modified syndrome polynomial is given. The decoding problem is viewed as an instance of a more general interpolation problem. The algorithm has the same computational complexity as the Berlekamp–Massey algorithm but is more efficient in hardware.

A new simple encoding technique that allows the design of almost all known block runlength-limited error control codes is described. Attention is focused on the most widely used codes (Hamming, Reed-Muller, Golay) with RLL properties. The trellis design procedure for the proposed codes is introduced. It is shown that the trellises of the designed codes are similar to the trellises of the coset codes designed by Forney (1988), and provide low-complexity soft maximum-likelihood performance.

An algorithm is presented for the decoding of triple-error-correcting binary b.c.h, codes. The algorithm is particularly suitable for parallel implementation and requires no invertors.

A new algorithm is given for the decoding of double-error-correcting binary b.c.h. codes. It can be rather simply implemented and is particularly suitable for parallel implementation.