Search

The principles of hardware compilation could be set to rewrite the rule book of silicon design. This article describes Handel-C, a parallel programming language that is providing programmers with a route to FPGA-based VLSI design, not by offering them a familiar programming environment combined with access to the parallel constructs familiar to the hardware designer, but by expressing the parallelism at a totally different level of abstraction; it doesn't describe the hardware like an HDL does - it describes the computation.

An emerging system design methodology in designing a reconfigurable HMAC-hash unit is utilised. This methodology directly maps a design described in a high-level language, Handel-C, to field programmable gate array platforms. The Handel-C approach narrows the gap between performance and flexibility and thus, reduces the risk of translating a high-level prototype into hardware description languages. It allows for a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. A detailed case study is considered: a reconfigurable HMAC-hash unit that implements six standard hash functions: MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1 and HMAC-RIPEMD-160. The performance of the designed unit has been enhanced by applying pipelining, parallelism and reconfigurability through the usage of the Handel-C methodology. The use of Handel-C resulted in the HMAC-hash unit architecture that is better in speed than most of the previously designed units. At the same time, the area cost for putting the six standard algorithms on the same hardware core is also kept to a minimum. It is found that the time required to design, implement and test the designed unit using this methodology is reasonably low compared with the time required using other design approaches.

CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an exemplar, pipelined design of the Karhunen-Loeve Transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs.

Forthcoming technology such as single-chip RISC/FPGA combinations make hardware compilation, fast prototyping and FPGA replacement of ASICs all more likely. FPGAs have made a software-oriented approach to digital design feasible. Remaining obstacles to this approach are reviewed. The trade-offs between use of an HDL and a C-variant, Handel-C, for logic synthesis are considered, particularly with regard to programmability and the overall design process. A simple example in a likely application area, simulation/emulation of telecommunications switches, illustrates the analysis.