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A hybrid radix-4/-8 truncated multiplier is proposed for mobile graphics processing unit (GPU) applications by combining the strong points of high-speed radix-4 and low-power radix-8 encoding schemes. A hybrid Booth encoder (HBE) for radix-4/-8 encoding is proposed by sharing the common logics between the two encodings. In addition, a hybrid radix-4/-8 truncation (HRT) scheme is proposed for more power reduction at a reasonable peak signal-to-noise ratio loss for mobile multimedia applications. Experimental results demonstrate 29.7 and 31.1% power savings from the HBE and the HRT schemes, respectively, resulting in a total of 60.7% power reduction from the previous work.

For flexible mapping of various task-level pipelines on a multi-core processor, the authors proposed the memory-centric network-on-chip (NoC). The memory-centric NoC manages producer-consumer data transactions between the tasks in the case of task-level pipelines are distributed over multiple processing cores. Since the memory-centric NoC manages the data transactions, it relieves burden of the software running on the processing cores and this results in power-efficient execution of task-level pipeline. To prove advantages of the memory-centric NoC, the authors implemented a multi-core processor based on the memory-centric NoC.

A 2.5 Gbit/s transimpedance amplifier is realised using a 0.6 /spl mu/m CMOS technology. By exploiting a regulated cascode configuration as the input stage, the amplifier achieves significant bandwidth improvement. The measured results demonstrate 2.2 GHz bandwidth for 0.5 pF photodiode capacitance with 55.3 dB/spl Omega/ transimpedance gain.

To save power consumption in read-modify-write (RMW) DRAM operation, a bit-wise read-compare-write (RCW) scheme is presented. Its power consumption depends on the number of bits that have to be updated by the bit-wise compare result between the read data and the modified data. If a random bit-wise update ratio is assumed, a 11.6% power saving is achieved when the proposed scheme is applied to the previous design.

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 /spl mu/m DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory.

A fast lock-on time mixed mode delay locked loop (DLL) is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.

A new charge transfer preamplifier scheme is developed for low power and high density DRAMs. It employs a boosting method with a MOSFET capacitor for a high voltage precharge level and a pulse control signal for a charge transfer switch. The new scheme increases the sensing margin and enhances the sensing speed under 1.5 V operation with a small area overhead. It also leads to a wider design window for a charge transfer switch as the supply voltage scales down.

A latchup resistant CMOS data output buffer for 0.5 µm CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adjusts its voltage level to suppress the leakage current. Its leakage current is controlled to be < 10 nA with the bonding pad voltage ranging from 0 to 10 V. The propagation delay is measured to be shorter by 3.8 ns than that of an NMOS data output buffer.

The fabrication and characterisation of two-dimensional phase-locked arrays of vertical cavity surface emitting lasers is reported. The three two-dimensional array structures characterised were a 2 × 3 periodic array of 10μm2 lasers, a hexagonal array and a centred hexagonal array of 5 μm hexagonal lasers. All arrays were fabricated using the same technique which was a combination of mesa etching and oxygen implantation isolation.

The coupling coefficient between two adjacent circular vertical cavity surface emitting lasers having an InGaAs strained quantum well active region (λg = 1μm) and a GaAs cavity has been analysed. The analysis was performed for Al0.3Ga0.7As cladding (n = 3.325) and air (n = 1). In order to obtain a coupling coeficient of 10−3, which is known for the stable phase locking of array, the laser separation must beless than 0.25μm for the lasers of radius 0.4μm with air cladding and be less than 0.72μm for the lasers of radius 1.2μm with Al0.3Ga0.7As cladding. Various structures of two-dimensional phase-locked arrays, such as periodic, circular and concentric circular arrays, can be realised by bringing lasers into close proximity of which value can be obtained from the analysis.