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An efficient common subexpression elimination algorithm is presented to reduce the area cost of realising the XOR-based operations for MixColumns, InvMixColumns, SubBytes, and InvSubBytes transformations in the Rijndael Advanced Encryption Standard (AES). This algorithm contains four optimisation priorities to extract the common factors in the bit-level equations. Performance comparisons in both the architecture-level design and the technology-dependent cell-based implementations are given. Experimental results show the authors proposed method reduces significantly the area cost of the whole AES processor design compared with synopsys area-optimised synthesis results or other previous implementations.

A new linear-array architecture for computation of both the discrete cosine transform (DCT) and the inverse DCT (IDCT) is derived from the heterogeneous dependence graphs representing the factorised coefficient matrices in the matrix formulation of the recursive algorithm. Using the Kronecker product representation of the order-recursive algorithm, it is observed that the kernel operations of the DCT and IDCT can be merged together by proper input/output data reordering. The processor containing only O(log/sub 2/N) stages is fully pipelineable and easily scaleable to compute longer DCT/IDCTs with transform length N to the power of two. Owing to the systematic matrix formulation and the corresponding efficient architectural design, the new DCT/IDCT processor has the advantages of high-throughput rate and low hardware cost. Furthermore, the power consumption can be reduced significantly by turning off the operation of the arithmetic units whenever possible.

A pass-transistor based cell library containing only two types of cells is designed and a corresponding logic/circuit synthesiser developed for logic mapping of any combinational circuit. The proposed design has better performance than the recently proposed lean integration with pass transistors (LEAP) cell library. Furthermore, the modified LEAP cell library can be easily migrated to a new process technology due to the smaller number of cells.

A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is presented. Owing to the reduction of the internal load capacitance, the counter and compressor have better speed and power performance than other recently proposed approaches.

The author presents VLSI implementation of a recently proposed quadratic-spline W-matrix transform (W-transform) to be used in multi-resolution image processing applications. The processor can compute W-transforms of any length (even or odd), rather than only those of a power of two length, as in most discrete wavelet transforms. The physical design of the processor based on a 0.6 /spl mu/m cell library is also included.