1. SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
- Author
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Lucas Compassi Severo, T. Ljubicic, A. Ruette, Agneta Oskarsson, G. Brulin, David Dobrigkeit Chinellato, Dionisio de Carvalho, David Olle Rickard Silvermyr, Lennart Osterman, S. Vereschagin, S.A. Zaporozhets, D. Moraes, Armando Ayala Pabón, P. Russo, Kenneth Francis Read, E. Wanlin, J. Adolfsson, Tiago Oliveira Weber, H.D. Hernandez Herrera, B.C.S. Sanches, Marcelo Gameiro Munhoz, Marco Bregant, Christophe Pierre Suire, V. Chambert, Ulf Mjörnmark, K.M.M. Tun-Lanoë, Bruno Espagnon, A. Pilyar, Arild Velure, Sohail Musa Mahmood, G. Noël, Ganesh Jagannath Tambave, C.L. Britton, W.A.M. Van Noije, Institut de Physique Nucléaire d'Orsay (IPNO), and Université Paris-Sud - Paris 11 (UP11)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS)
- Subjects
Digital signal processor ,Computer science ,Analog-to-digital converter ,02 engineering and technology ,Integrated circuit design ,01 natural sciences ,law.invention ,ALICE ,Application-specific integrated circuit ,law ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,[PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] ,Instrumentation ,Mathematical Physics ,010308 nuclear & particles physics ,business.industry ,Amplifier ,020208 electrical & electronic engineering ,Electrical engineering ,sensitivity ,Chip ,electronics: upgrade ,time projection chamber ,Upgrade ,analog-to-digital converter ,CMOS ,amplifier ,electronics: readout ,integrated circuit: design ,business ,Computer hardware ,muon: spectrometer - Abstract
International audience; This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.
- Published
- 2017
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